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PDF CDP68HC68T1 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68T1 | |
| Descripción | CMOS Real-Time Clock | |
| Fabricantes | GE | |
| Logotipo |  |
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CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _""-
CDP68HC68T1
Advance Information
eLK OUT
CPUR
INT
SCK
"'CSI
MISO
CE
VSS
16 Voo
15 XTAL OUT
3 14 XTAL IN
4 13 V BATT
5 12 vSYS
6 II LINE
10 PaR
8 9 PSE
TOP VIEW
92CS-380~3
TERMINAL
ASSIGNMENT
CMOS Real-Time Clock with
RAM and Power Sense/Control
Feature.:
• SPI (Serial Peripheral Interface)
• Full clock features: sec., min., hrs.
(12/24, AM/PM), day of week,
date, month, year, (0-99), auto
leap year
• 32-word x 8-bit RAM
• Seconds, minutes, hours alarm
• Automatic power loss detection
• Minimum standby (timekeeping)
voltages: 2.2 volts
• Selectable crystal or 50/60-Hz line input
• Buffered clock output
• Battery input pin that powers oscillator
and also connects to the Voo pin when
main power fails
• Three independent interrupt modes:
alarm, periodic or power-down sense
The COPS8HCS8T1, real-time clock provides a time/calen-
dar function, a 32 byte static RAM and a 3-wire serial
peripheral interface (SPI bus). The primary function of the
clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. Th~ clock
either operates with a 32+kHz, 1+MHz, 2+MHz or 4+MHz
crystal or it can be driven by an external clock source atthe
same frequencies. In addition, the frequency can be selected
to allow operation from a 50 or SO-Hz input. The time
registers furnish seconds, minutes, and hours data while
the calendar registers offer day of week, date, month and
year information. The data In the time/calendar registers is
in BCD format. In addition, 12 or 24-hour operation can be
selected with an AM-PM Indicator available in the 12-hour
mode. The T1 has a separate clock output that supplies one
of 7 selectable frequencies.
Computer handshaking is established with a "wired or"
interrupt output. The interrupt can be activated by anyone
of three separate internal sources. The first is an alarm
circuit that consists of seconds, minutes and hours alarm
latches that trigger the interrupt when they are in coinci-
dence with the value in the seconds, minutes and hours time
counters. The second interrupt source Is one of 15 periodic
signals that range from subsecond to daily Intervals. The
final Interrupt source is from the power-sense circuitthat is
used with the LINE input pin to monitor power failures. Two
other pins, the power supply enable (PSE) output and the
Vsys input are used for external power control. The CPUR
reset output pin is available for power-down operation and
is activated under software control. CPUR Is also activated
by a watchdog circuit that if enabled requires the CPU to
toggle the CE pin periodically without a serial data transfer.
The COPS8HCS8T1 Is available in a 1S-lead hermetiC dual-
in-line ceramic package (0 suffix), in a 1S-lead dual-in-line
plastic package (E suffix), and in a 20-lead small-outline
plastic package (M suffix).
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to V•• terminal) ....................................................................................-0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS EXCEPT LINE .....•••••••.........••...•.••.•..•••........••••••..••...•• -0.5 to Voo +0.5 V
V••• S Voc + 1.5 V
DC INPUT CURRENT. ANY ONE INPUT (LINE INPUT, -10 mAl ............................................................ ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA =+60 to +85·C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/·C to 200 mW
For T. =-55 to +100·C (PACKAGE TYPE D) .............................................................................. 500 mW
For T. =+100 to +125·C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/·C to 200 mW
ForTA =-40· to +70·C (PACKAGE TYPE M)' .:.......................................................................... 400 mW
ForTA =+70· to +85·C (PACKAGE TYPE M)· ............................................ ·· Derate linearly at 6.0 mW/·C to 310 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................... 40 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ............................................................................................... -55 to +125· C
PACKAGE TYPE E and M .......................................................................................... -40 to +85·C
STORAGE-TEMPERATURE RANGE (T...) ........................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 In. (1.59 ± 0.79 mm) from case for 10 s max. .. ................................................... +265· C
• Printed-circuit board mount: 57 mm x 57 mm minimum area x 1.6 mm thick G1 0 epoxy glass. or equivalent
File Number 1547
542 ______________________________________________________
1 page  
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC68T1
PROGRAMMERS MODEL - CLOCK REGISTERS
I IHEX ADDRESS
WRITE/READ REGISTERS
DB7
DBO
NAME
SECONDS (00-59)---
20
TENS 0-5
21
12 PM/AM
22
HR. X TENS 0-2
24
X X XX
23
TENS 0-3
24
25
DB7,1 = 12 HR, 0 = 24 HR
DB5 =1 PM,O =AM
HOURS (01-12 OR 00-23)
SUNDAY = 1
DAY OF WK (01-07) - - -
01-28
(DATE)
DAY OF
MONTH
(
2
9~~) -
JAN = 1
MONTH (01-12)- DEC = 12-
26
7
31
YEARS (00-99) - - - -
CONTROL-----
7
32
INTERRUPT-----
WRITE ONLY REGISTERS
28
TENS 0-5
UNITS 0-9
ALARM SECONDS (00-59) -
29
TENS 0-5
UNITS 0-9
ALARM MINUTES (00-59)-
ALARM HOURS (01-12 or 00-23)
2A
PLUS AM/PM IN 12 HR. MODE
PM = 1, AM = 0
READ ONLY REGISTER
30 STATUS
NOTE: X = DON'T CARE WRITES r---------::-:::-------------
X = 0 WHEN READ
7 6 5 BIT4 3 2 1 0
RAM DATA BYTE
07 1 06 1 OS 1 04 103 1 02 101 1 DO I
HEX ADDRESS 00-1F
82CM·31011
546 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
5 Page 
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC68T1
SERIAL PERIPHERAL INTERFACE (SPI)
PIN SIGNAL DESCRIPTION
SCK (Serial Clock Input)· - This input causes serial data to
be latched from the MOSI input and shifted out on the MISO
output.
MOSI (Master Out/Slave In)· - Data bytes are shifted in at
this pin, most significant bit (MSB) first.
MISO (Malter In/Slave Out) - Data bytes are shifted out at
this pin, most signficant bit (MSB) first.
CE (Chip Enable)·· - A positive chip-enable input. A low
level at this Input holds the serial interface logic in a reset
state, and disables the output driver at the MISO pin.
• These inputs will retain their previous state ilthe line driving them
goes into a High-Z state.
•• The CE Input has as internal pull-down device-ilthe input Is In a
low state before going to 8 High Z, the input can be left in 8 High Z.
TRUTH TABLE
MODE
CE
SCK
SIGNAL
MOSI
MISO
DISABLED
RESET
L INPUT
DISABLED
INPUT
DISABLED
HIGHZ
WRITE
JH CPOL = 1
DATA BIT
HIGHZ
~CPOL=O
LATCH
READ
~H CPOL = 1
X
---'CPOL=O
NEXT DATA
BIT SHIFTED
OUT.c.
.c. MISO remains at a High Z until 8 bits of data are ready to be shifted out during a READ. It remains at a High Z during
the entire WRITE cycle.
FUNCTIONAL DESCRIPTION
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the
microcomputer, is active only during address and data
transfers In systems using the CDP68HC05C4 or
CDP68HC05D2, the inactive clock polarity is determined by
the CPOL bit in the microcomputer's control register. A
unique feature of the CDP68HC68T1 is that itautomatica"y
determines the level of the inactive clock I:>y sampling SCK
when CE becomes active (see Fig. 8). Input data (MOSI) is
latched internally on the Internal Strobe edge and output
data (MISO) is shifted out on the Shift edge, as defined by
Fig. 8. There is one clock for each data bit transferred
(address as we" as data bits are transferred in groups of 8).
E
CPOL- I {
SCK
t_ _ _ _-J SHIFT
CPOL.O{E
SCK
+
trlNSTTERRONBEALtl
MOSl: _ _ _ _ _ _-{
NOTE: "CPOLII IS A BIT THAT IS SET IN THE
MICROCOMPUTER'S CONTROL REGISTER
92CS-37945
Fig. 8 - Serial RAM clock (SCK) as a function of MCU clock
polarity (CPOL).
552 ______________________________________________
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68T1.PDF ] | |
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