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PDF ACX567AKM-7 Data sheet ( Hoja de datos )
| Número de pieza | ACX567AKM-7 | |
| Descripción | HVGA Transflective color LCD Module | |
| Fabricantes | Sony | |
| Logotipo |  |
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Distribution Internal Outside
Restraint Prohibited Prohibited
7.96cm 320 480 16,777,216 colors HVGA Transflective color LCD Module
ACX567AKM-7
Description
This display is a 7.96cm diagonal active matrix transflective color LCD module based on Low temperature
polycrystalline silicon TFT technology. This LCD has 320 480 pixels and integrated driver which provides a
symmetric module with narrow edge frame. This module includes a LED backlight and a memory integrated
one chip driver IC with Low power consumption. The driver IC contains FL3G/SPI and RGB interface circuit,
partial memory, CABC function and DC-DC converter.
(Application: Smartphone)
Features
LCD type
Dot layout
Number of dots
Dot size
Number of colors
Interface
Partial RAM size
Supply voltage
Low power consumption
High reflectivity
High contrast ratio
Luminance (LED backlight on)
Built-in DC-DC converter
Weight
: Transflective
Symmetric and narrow frame edge module
: RGB stripe
: 320 RGB 480 / Portrait type
: 0.046mm 0.138mm (184ppi)
: 16,777,216 (R,G, B each 8bit)
: 8bit FL3G/SPI or RGB
: 320 120 3bit
: VDD_18 1.8V 5%
VDD (VBATT) 3.0V 3%
: 32mW (max.) (Vertical B/W worst image @VBATT = 3.7V)
100 W (max.) (Standby mode)
: 1.7% (@Diffusion)
: 700:1 (typ.) (LED backlight on)
: 400cd/m2 (typ.)
: 15g
SonyProhibited Prohibited reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E08Z19-SP
1 page  
ACX567AKM-7
Pin Description
Pin No.
Symbol
1 N.C.
2 BL LED ANODE
3 BL LED CATHODE
4 SPI_CS
5 PWM_LCD
6 SPI_DI/DO
7 N.C.
8 GND
9 N.C.
10 GND
11 GND
12 FL3G D0–
13 SPI_CLK
14 FL3G D0+
15 GND
16 GND
17 RESETX
18 FL3G CK–
19 GND
20 FL3G CK+
21 VBATT
22 GND
23 VBATT
24 FL3G D1–
25 VDD_18
26 FL3G D1+
27 VDD_18
28 GND
29 NVM
30 N.C.
I/O Description
Non connect. For customer, this pin should be open.
Common anode for LED's
Common cathode for LED's
I Serial interface CHIP SET input
O PWM signal output for LCD
I/O Serial interface DATA input/output
Non connect. For customer, this pin should be open.
Ground
Non connect. For customer, this pin should be open.
Ground
Ground
I Negative polarity signal of High-speed data channel 0
I Serial interface clock input
I Positive polarity signal of High-speed data channel 0
Ground
Ground
I Hard reset input. (Active-Low)
I Negative polarity signal of High-speed clock channel
Ground
I Positive polarity signal of High-speed clock channel
P Positive power supply 3.0V
Ground
P Positive power supply 3.0V
I Negative polarity signal of High-speed data channel 1
P Positive power supply 1.8V
I Positive polarity signal of High-speed data channel 1
P Positive power supply 1.8V
Ground
Non connect. For customer, this pin should be open.
Using SONY's manufactory only.
Non connect. For customer, this pin should be open.
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5 Page 
ACX567AKM-7
Input Timing
FlatLink3G Interface
Introduction
The number of data channels between TX and RX is programmable from 1 to 2 depending on bandwidth
needed. The data link speed is defined according to pixel clock (PCLK) of RGB I/F and the number of data
channels. FlatLink3G has 2 different power modes; shutdown and active. In shutdown mode, FlatLink3G
is totally inactive and assumed to consume least power (order of A). In active mode, FlatLink3G works as
a High-speed data link as defined.
TX adds odd parity bit in every data frame and RX checks the pixel data according to the sent parity.
System Block Diagram and Link Protocol
System Block Diagram of FlatLink3G
FlatLink3G consists of three parts; TX, RX and High-speed signaling channels, as shown below.
SET Side
IC Side
VDDI
VDD
V3G_LDO
Receiver Block (RX)
To Internal Circuit
RX_CPO
RX_LS
RX_SD
D1+/D1–
D0+/D0–
8 RX_R[7:0]
8 RX_G[7:0]
8 RX_B[7:0]
3 RX_HS, VS, DE
PLL CLK+/CLK1–
PLL RX_PCLK
VDD_PLL
VDDI is a link power and logic level supply and GND is a ground level of all circuits from a system power
supply.
TX_R[7:0], TX_G[7:0], TX_B[7:0], TX_VS, TX_HS, TX_DE and TX_PCLK are RGB I/F parallel CMOS
signals provided for TX. PLL of TX provides necessary multiplied clock internally based on TX_PCLK.
TX serializes TX_R[7:0], TX_G[7:0], TX_B[7:0], TX_VS, TX_HS and TX_DE into High-speed data
channels, D0+/D0–, D1+/D1–, D2+/D2–, based on the multiplied clock. TX transfers TX_PLCK into a
High-speed clock channel, CLK+/CLK–, with its original rate. The number of data channels is
programmed by TX_LS and RX_LS.
PLL of RX provides necessary multiplied clock internally based on the High-speed clock channel
inputs. RX desterilizes the High-speed data channel inputs into RX_R[7:0], RX_G[7:0], RX_B[7:0],
RX_VS, RX_HS and RX_DE based on the multiplied clock. TX transfers the High-speed clock channel
into RX_PCLK. RX_R[7:0], RX_G[7:0], RX_B[7:0], RX_VS, RX_HS, RX_DE and RX_PCLK construct
RGB I/F parallel CMOS signals as output.
RX_XSD are CMOS signals for shutdown of TX and RX.
- 11 -
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