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PDF UPD6514-1 Data sheet ( Hoja de datos )
| Número de pieza | UPD6514-1 | |
| Descripción | 1024 x 4 BIT STATIC CMOS RAM | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEe Microcomputers, Inc.
NEe
fL PD444/6514
fL PD444/6514·1
fL PD444/6514·2
fL PD444/6514·3
1024 x 4 BIT STATIC CMOS RAM
OESCR IPTION
The /JPD444/6514 is a high-speed, low power silicon gate CMOS 4096-bit static RAM
organized 1024 words by 4 bits_ It uses DC stable (static) circuitry throughout and
therefore requires no clock or refreshing to operate_ Data access is particularly simple
since address setup times are not required. The data is read out nondestructively and
has the same polarity as the input data. Common input/output pins are provided.
CSCS controls the power down feature_ In less than a cycle time after goes high -
deselecting the /JPD444/6514 - the part automatically reduces its power requirements
and re~ins in this low power standby mode as long as Cs is high. There is no mini-
mum CS high time for device operation, although it will determine the length of time
in the power down mode. When CS goes low, selecting the /JPD444/6514, the
/JPD444/6514 automatically powers up_
The /JPD444/6514 is placed in an 18-pin plastic package for the highest possible
density _It is directly TTL compatible in all respects: inputs, outputs, and a single
+5V supply_ The /JPD444/6514 is pin-compatible with the /JPD2114L NMOS Static
RAM.
Data retention is guaranteed to 2 volts on all parts. These devices are ideally suited
for low power applications where battery operation or battery backup for non-
volatility are required.
FEATU RES
• Low Power Standby - 5 /JW Typ.
• Low Power Operation
• Data Retention - 2.0V Min_
• Capability of Battery Backup Operation
• Fast Access Time - 200-450 ns
• Identical Cycle and Access Times
• Single +5V Supply
• No Clock or Timing Strobe Required
• Completely Static Memory
• Automatic Power-Down
• Directly TTL compatible: All Inputs and Outputs
• Common Data Input and Output using Three-State Outputs
• Replacement for /JPD2114L and Equivalent Devices
• Available in a Standard 18-Pin Plastic Package
PIN CONFIGURATION
AS
AS
A4
Aa
AO
A1
A2
CS
GND
Vee
A7
AS
Ag
1/01
1/02
I/0a
1/04
WE
• PIN NAMES
AO-A9
WE
CS
1/0 1-1/0 4
VCC
GND
Add ress Inputs
Write Enable
Chip Select
Data Input/Output
Power (+5V)
Ground
Rev/l
89
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet UPD6514-1.PDF ] | |
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| UPD6514-3 | 1024 x 4 BIT STATIC CMOS RAM | NEC |
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