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PDF UPD8039L Data sheet ( Hoja de datos )
| Número de pieza | UPD8039L | |
| Descripción | HIGH PERFORMANCE SINGLE CHIP 8-BIT MICROCOMPUTERS | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD8039L (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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NEe Microcomputers, Inc.
NEe
p.PD8049
p.PD8039L
HIGH PERFORMANCE
SINGLE CHIP8-BIT MICROCOMPUTERS
DESCRIPTION
The NEC /.IPDS049 and /.IPDS039L are single chip 8-bit microcomputers. The processors
differ only in their internal program memory options: the /.IPDS049 has 2K x S bytes
of mask ROM and the /.IPDS039L has external program memory. Both of these devices
feature new, high performance 11 MHz operation.
F EATU R ES
• High Performance 11 MHz Operation
• Full',' Compatible with Industry Standard S049/S039
• Pin Compatible with the./.IPD8048/S74S/S035
• :'JMOS Silicon Gate Technology Requiring a Single +5V ±10%Supply
• 1.36/.1s Cycle Time. All Instructions 1 or 2 Bytes
• Programmable Interval Timer/Event Counter
• 2K x 8 Bytes of ROM, 12S x S Bytes of RAM
• Single Level Interrupt
• 96 Instructions: 70 Percent Single Byte
• 27 I/O Lines
• Internal Clock Generator
• Expandable with SOSOA/SOS5A Peripherals
• Available in Both Ceramic and Plastic 40-Pin Packages
PIN CONFIGURATION
TO
XTALl
XTAL2
RESEsTs
INT
EA
RD
PsEN
WR
ALE
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
Vss
/.IPD
8049/
8039L
Vee
Tl
P27
P26
P25
P24
P17
P16
P15 .
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P21
P20
II
357
1 page  
}L:PD8049/803IL
AC CHARACTERISTICS
READ, WRITE AND INSTRUCTION FETCH - EXTERNAL
DATA AND PROGRAM MEMORY
Ta 0' C to +70"C; VCC c VDD ~ +5V ± 10%; VSS ~ OV
LIMITS
PARAMETER
SYMBOL MIN TYP MAX
ALE Pulse Width
tLL
Address Setup before ALE
tAL
Address Hold from ALE
tLA
Control Pulse Width IPSEN, RD, WRI
tcc
Data Setup before WR
tnw
Data Hold after WR
two
Cycle Time
tCY
Data Hold
tOR
PSEN, RD to Data In
tRD
Address Setup before WR
tAW
Address Setup before Data In
tAD
Address Float to RD, PSEN
tAFC
CDNotes
For Control Outputs: CL = 80 pF
@ For Bus Outputs CL = 150 pF
150
70
50
300
250
40
1,36
0
200
-40
15,0
100
200
400
@ tCY = 1,361's
PORT 2 TIMING
T a = O'c to +70'C; Vcc = +5V ± 10%; VSS = OV
UNIT
ns
ns
ns
ns
ns
ns
I'S
ns
ns
ns
ns
ns
TEST
CONDITIONS
CL=20pF@
PARAMETER
Port Control Setup before Failing
Edge of PROG
Port Control Hold after Failing
Edge of PROG
PROG to Time P2 I nput must be
Valid
Output Data Setup Time
Output Data Hold Time
Input Data Hold Time
PROG Pulse Width
Port 2 110 Data Setup
Port 2 1/0 Data Hold
SYMBOL
LIMITS
TEST
MIN TYP MAX UNIT CONDITIONS
tcp 100
ns
tpr: 60
ns
tpR
top 200
tpD 20
tPF 0
tpp 700
tPL 150
tLP 20
650 ns
ns
ns
150 ns
ns
ns
ns
II
TIMING WAVEFORMS
ALE
t---~tLL~-tCY-~·1
~ ~I____________~I--~L_
BUS
FLOATING
INSTRUCTION FETCH FROM EXTERrlAL MEMORY
361
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UPD8039L.PDF ] | |
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