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UPD780-1 fiches techniques PDF

NEC - 8-BIT N-CHANNEL MICROPROCESSOR

Numéro de référence UPD780-1
Description 8-BIT N-CHANNEL MICROPROCESSOR
Fabricant NEC 
Logo NEC 





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UPD780-1 fiche technique
NEe Microcomputers, Inc.
NEe
J.L PD780
J.L PD780·1
8·BIT N·CHANNEL MICROPROCESSOR
COMPLETELY Z80™ COMPATIBLE
DESC RIPTI ON
The pPD780 and pPD780-1 processors are single-chip microprocessors developed from
third-generation technology,Their increased computational power produces higher
system through-put and more efficient memory utilization, surpassing that of any
second-generation microprocessor, The single voltage requirement of the t1PD780 and
IlPD780-1 processors makes it easy to implement them into a system. All output sig-
nals are fully decoded and timed to either standard memory or peripheral circuits. An
N-channel, ion-implanted, silicon gate MOS process is utilized in implementing the
circuit.
The block diagram shows the functions of the processor and details the internal register
structure. The structure contains 26 bytes of Read/Write (R/W) memory available to
the programmer. Included in the registers are two sets of six general purpose registers,
which may be used individually as S-bit registers, or as 6-bit register pairs. Also
included are two sets of accumulator and flag registers.
Through a group of exchange instructions the programmer has access to either set of
main or alternate registers. The alternate register permits foreground/background mode
of operation, or may be u~ed fv( fast interrupt response. A l6-bit stack pointer is also
included in each processor, simplifying implementation of multiple level interrupts,
permitting unlimited subroutine nesting, and simplifying many types of data handling.
The two 16-bit index registers simplify implementation of relocatable code and manipu-
lation of tabular data. The refresh register automatically refreshes external dynamic
memories. A powerful interrupt response mode uses the I register to form the
upper 8 bits of a pointer to an interrupt service address table, while the interrupting
apparatus supplies the lower 8 bits of the pointer. An indirect call will then be made to
service this address.
FEATU RES
Single Chip, N-Channel Silicon Gate Processor
• 158 Instructions - Including all 78 of the 8080A Instructions, Permitting Total
Software Compatibility
• New 4-,8-, and 16-8it Operations Featuring Useful Addressing Modes such as
Indexed, Bit and Relative
• 17 Interndl Registers
• Three Modes of Rapid Interrupt Response, and One Non-Maskable Interrupt
• Directly Connects Standard Speed Dynamic or Static Memories, with Minimum
Support Circuitry
• Single-Phase +5 Volt Clock and 5 VDC Supply
• TTL Compatibility
• Automatic Dynamic RAM Refresh Circuitry
• Available in Plastic Package
PIN CONFIGURATION
A11
A'2
A13
A'4
A'5
¢
D4
D3
D5
D6
+5V
02
D7
00
0,
INT
NMI
HALT
MREO
IORO
4
5
6
10
11
12
13
14
15
16
17
18
pPD
780/
780-1
A10
39 A9
38 A8
37 A7
:36 A6
35 A5
34 A4
33 A3
32 A2
31 A,
30 AO
29 GNO
28 RFSH
27 M,
26 RESET
25 BUSRO
24 WAIT
23 BUSAK
22 WR
21 AD
II
TM:Z80 is a registered trademark of Zilog, Inc_
367-

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