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PDF MG82FE564 Data sheet ( Hoja de datos )

Número de pieza MG82FE564
Descripción 8051-Based MCU
Fabricantes Megawin　
Logotipo Megawin Logotipo



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No Preview Available ! MG82FE564 Hoja de datos, Descripción, Manual

8051-Based MCU
MG82FE/L564
Data Sheet
Version: A1.01
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2012 All rights reserved.
2015/09 version A1.01

1 page




MG82FE564 pdf
Content
Features............................................................................................................. 3
Content .............................................................................................................. 5
1. Description..................................................................................................... 9
2. Order information........................................................................................... 9
3. Pin Description ............................................................................................ 10
3.1. Pin Definition ................................................................................................................10
3.2. Package Configuration .................................................................................................13
4. Block Diagram ............................................................................................. 15
5. Special Function Register ............................................................................ 16
5.1. SFR Map ......................................................................................................................16
5.2. SFR Bit Assignment .....................................................................................................17
6. Memory Organization .................................................................................. 19
6.1. On-Chip Program Flash................................................................................................19
6.2. On-Chip Data RAM.......................................................................................................20
6.3. On-chip expanded RAM (XRAM)..................................................................................24
6.4. External Data Memory access ......................................................................................25
6.4.1.
Multiplexed Mode for 8-bit MOVX .........................................................................................26
6.4.2.
Multiplexed Mode for 16-bit MOVX .......................................................................................27
6.4.3.
No Address Phase Mode for MOVX .....................................................................................28
7. 8051 CPU Description ................................................................................. 29
7.1. CPU Register ...............................................................................................................29
7.2. CPU Timing ..................................................................................................................30
7.3. CPU Addressing Mode .................................................................................................30
7.4. Declaration Identifiers in a C51-Compiler .....................................................................31
8. Dual Data Pointer Register (DPTR) ............................................................. 32
9. Configurable I/O Ports ................................................................................. 33
9.1. IO Structure ..................................................................................................................33
9.1.1.
Quasi-Bidirectional IO Structure ...........................................................................................33
9.1.2.
Push-Pull Output Structure ...................................................................................................34
9.1.3.
Input-Only (High Impedance Input) Structure .......................................................................34
9.1.4.
Open-Drain Output Structure ................................................................................................35
9.2. I/O Port Register...........................................................................................................35
9.2.1.
Port 0 Register ......................................................................................................................36
9.2.2.
Port 1 Register ......................................................................................................................36
9.2.3.
Port 2 Register ......................................................................................................................36
9.2.4.
Port 3 Register ......................................................................................................................37
9.2.5.
Port 4 Register ......................................................................................................................37
9.2.6.
Port 5 Register ......................................................................................................................38
9.2.7.
Port 6 Register ......................................................................................................................38
9.3. Alternate Function Redirection......................................................................................38
9.4. GPIO Sample Code......................................................................................................40
10.Interrupt ....................................................................................................... 41
10.1.
10.2.
10.1.
Interrupt Structure.........................................................................................................41
Interrupt Register..........................................................................................................43
Interrupt Sample Code..................................................................................................48
11.Timers/Counters .......................................................................................... 49
11.1. Timer0 and Timer1 .......................................................................................................49
11.1.1. Mode 0 Structure ..................................................................................................................49
11.1.2. Mode 1 Structure ..................................................................................................................50
11.1.3. Mode 2 Structure ..................................................................................................................50
11.1.4. Mode 3 Structure ..................................................................................................................51
11.1.5. Timer Clock-Out Structure ....................................................................................................51
MEGAWIN
MG82FEL564 Data Sheet
5

5 Page





MG82FE564 arduino
P2.0
(A8)
(KBI0)
P2.1
(A9)
(KBI1)
P2.2
(A10)
(KBI2)
P2.3
(A11)
(KBI3)
P2.4
(A12)
(KBI4)
P2.5
(A13)
(KBI5)
P2.6
(A14)
(KBI6)
P2.7
(A15)
(KBI7)
P3.0
(RXD0)
P3.1
(TXD0)
P3.2
(nINT0)
P3.3
(nINT1)
P3.4
(T0)
(T0CKO)
P3.5
(T1)
(T1CKO)
P3.6
(nWR)
P3.7
(nRD)
P4.0
P4.1
P4.2
(nINT3)
P4.3
(nINT2)
P4.4
(OCD_SCL)
P4.5
P4.6
(ALE)
P5.0
P5.1
P5.2
P5.3
P6.0
MEGAWIN
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
-
-
-
-
29
31
30
--
--
--
--
18
18 20
19 21
20 22
21 23
22 24
23 25
24 26
25 27
56
78
89
9 10
10 11
11 12
12 13
13 14
17 19
28 31
39 43
67
26 28
29 32
27 30
-- 15
-- 29
-- 41
-- 4
14 16
I/O * Port 2.0.
* A8: A8 output during external data memory access.
* KBI0: keypad input 0.
I/O * Port 2.1.
* A9: A9 output during external data memory access.
* KBI1: keypad input 1.
I/O * Port 2.2.
* A10: A10 output during external data memory
access.
* KBI2: keypad input 2.
I/O * Port 2.3.
* A11: A11 output during external data memory
access.
* KBI3: keypad input 3.
I/O * Port 2.4.
* A12: A12 output during external data memory
access.
* KBI4: keypad input 4.
I/O * Port 2.5.
* A13: A13 output during external data memory
access.
* KBI5: keypad input 5.
I/O * Port 2.6.
* A14: A14 output during external data memory
access.
* KBI6: keypad input 6.
I/O * Port 2.7.
* A15: A15 output during external data memory
access.
* KBI7: keypad input 7.
I/O * Port 3.0.
* RXD0: UART0 serial input port.
I/O * Port 3.1.
* TXD0: UART0 serial output port.
I/O * Port 3.2.
* nINT0: external interrupt 0 input.
I/O * Port 3.3.
* nINT1: external interrupt 1 input.
I/O * Port 3.4.
* T0: Timer/Counter 0 external input.
* T0CKO: programmable clock-out from Timer 0.
I/O * Port 3.5.
* T1: Timer/Counter 1 external input.
* T1CKO: programmable clock-out from Timer 1.
I/O * Port 3.6.
* nWR: external data memory write strobe.
I/O * Port 3 bit-7.
* nRD: external data memory read strobe.
I/O * Port 4.0.
I/O * Port 4.1.
I/O * Port 4.2.
* nINT3: external interrupt 3 input.
I/O * Port 4.3.
* nINT2: external interrupt 2 input.
I/O * Port 4.4.
* OCD_SCL: OCD interface, serial clock.
I/O * Port 4.5.
* OCD_SDA: OCD interface, serial data.
I/O * Port 4.6.
* ALE: Address Latch Enable, output pulse for latching
the low byte of the address during an access cycle to
external data memory.
I/O * Port 5.0.
I/O * Port 5.1.
I/O * Port 5.2
I/O * Port 5.3
I/O * Port 6.0. It is only accessed in SFR page ―F‖.
MG82FEL564 Data Sheet
11

11 Page







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