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PDF MG84FG516 Data sheet ( Hoja de datos )
| Número de pieza | MG84FG516 | |
| Descripción | 8051-Based MCU | |
| Fabricantes | Megawin | |
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8051-Based MCU
MG84FG516
Data Sheet
Version: A1.5
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2005 All rights reserved.
2015/09 version A1.5
1 page  
Content
Features............................................................................................................ 3
Content ............................................................................................................ 5
1. General Description.................................................................................. 11
2. Ordering Information................................................................................. 12
3. Block Diagram .......................................................................................... 13
4. Special Function Register......................................................................... 14
4.1. SFR Map (Page 0~F) ..........................................................................................14
4.2. SFR Bit Assignment (Page 0~F) .........................................................................16
4.3. Auxiliary SFR Map (Page P) ...............................................................................19
4.4. Auxiliary SFR Bit Assignment (Page P)...............................................................20
5. Pin Configurations .................................................................................... 21
5.1. Package Instruction.............................................................................................21
5.2. Pin Description ....................................................................................................23
5.3. Alternate Function Redirection ............................................................................26
6. 8051 CPU Function Description ............................................................... 28
6.1. CPU Register ......................................................................................................28
6.2. CPU Timing.........................................................................................................29
6.3. CPU Addressing Mode........................................................................................29
7. Memory Organization ............................................................................... 31
7.1. On-Chip Program Flash ......................................................................................31
7.2. On-Chip Data RAM .............................................................................................32
7.3. On-chip expanded RAM (XRAM) ........................................................................36
7.4. External Data Memory access ............................................................................37
7.4.1. Multiplexed Mode for 8-bit MOVX............................................................................... 38
7.4.2. Multiplexed Mode for 16-bit MOVX ............................................................................. 39
7.4.3. No Address Phase Mode for MOVX ........................................................................... 40
7.5. Declaration Identifiers in a C51-Compiler............................................................41
8. Dual Data Pointer Register (DPTR) .......................................................... 42
9. System Clock ........................................................................................... 43
9.1. Clock Structure....................................................................................................43
9.2. Clock Register .....................................................................................................44
9.3. Clock Sample Code.............................................................................................47
10. Watch Dog Timer (WDT) .......................................................................... 50
10.1. WDT Structure ....................................................................................................50
10.2. WDT During Idle and Power Down .....................................................................50
10.3. WDT Register......................................................................................................51
10.4. WDT Hardware Option ........................................................................................52
10.5. WDT Sample Code .............................................................................................53
11. System Reset ........................................................................................... 55
11.1. Reset Source ......................................................................................................55
11.2. Power-On Reset..................................................................................................55
11.3. External Reset.....................................................................................................56
11.4. Software Reset....................................................................................................56
11.5. Illegal Address Reset ..........................................................................................56
11.6. Brown-Out Reset.................................................................................................56
11.7. WDT Reset..........................................................................................................57
MEGAWIN
MG84FG516 Data Sheet
5
5 Page 
1. General Description
The MG84FG516 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051
compatible instruction set. Therefore at the same performance as the standard 8051, the MG84FG516 can operate
at a much lower speed and thereby greatly reduce the power consumption.
The MG84FG516 has 64K bytes of embedded Flash memory for code and data. The Flash memory can be
programmed either in serial writer mode (via ICP, In-Circuit Programming) or in In-System Programming mode (via
USB DFU). And, it also provides the In-Application Programming (IAP) capability. ICP and ISP allow the user to
download new code without removing the microcontroller from the actual end product; IAP means that the device
can write non-volatile data in the Flash memory while the application program is running. There needs no external
high voltage for programming due to its built-in charge-pumping circuitry.
The MG84FG516 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, four 8-bit I/O ports,
two external interrupts, a multi-source 4-level interrupt controller, a serial port (UART0) and three timer/counters. In
addition, the MG84FG516 has a full speed USB device function, three extra I/O ports (P4[6:0], P5, P6), one XRAM
of 4096 bytes, two extra external interrupts with High/low trigger option, 12-bit ADC, a 6-channel PCA, SPI, TWSI,
secondary serial port (UART1), keypad interrupt, Watchdog Timer, 4th 16-bit timer, two Brown-out Detectors, an
on-chip crystal oscillator(shared with P6.0 and P6.1), an internal high precision oscillator to fit USB full speed
application, an internal low speed RC oscillator (ILRCO) and an enhanced serial function in UART0 that facilitates
multiprocessor communication and a speed improvement mechanism (X2/X4 mode).
The MG84FG516 has multiple operating modes to reduce the power consumption: idle mode, power down mode,
slow mode, sub-clock mode, watch mode and monitor mode. In the Idle mode the CPU is frozen while the
peripherals and the interrupt system are still operating. In the Power-Down mode the RAM and SFRs‟ value are
saved and all other functions are inoperative; most importantly, in the Power-down mode the device can be waked
up by many interrupt or reset sources. In slow mode, the user can further reduce the power consumption by using
the 8-bit system clock pre-scaler to slow down the operating speed. Or select sub-clock mode which clock source is
derived from internal low speed oscillator (ILRCO) for CPU to perform an ultra low speed operation. In watch mode,
it keeps WDT running in power-down or idle mode and resumes CPU when WDT overflows. Monitor mode provides
the Brown-Out detection in power down mode and resumes CPU when chip VDD reaches the specific detection
level.
Additionally, the MG84FG516 is equipped with the Megawin proprietary On-Chip Debug (OCD) interface for
In-Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any
target resource occupied. Several operations necessary for an ICE are supported such as Reset, Run, Stop, Step,
Run to Cursor and Breakpoint Setting. The user has no need to prepare any development board during firmware
developing or the socket adapter used in the traditional ICE probe head. All the thing the user needs to do is to
prepare a connector for the dedicated OCD interface. This powerful feature makes the developing very easy for any
user.
MEGAWIN
MG84FG516 Data Sheet
11
11 Page | ||
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