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PDF UPD765 Data sheet ( Hoja de datos )
| Número de pieza | UPD765 | |
| Descripción | SINGLE/DOUBLE DENSITY FLOPPY DISK CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD765 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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NEe Microcomputers, Inc.
NEe
/LPD765
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
DESCRIPTION
FEATURES
PIN CONFIGURATION
TM:Z80 is. registered tredemark of Zilog, Inc,
The J,tPD765 is an LSI Floppy Disk Controller (FDC) Chip, which contains the circuitry and control
functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either
IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
double sided recording. The J,tPD765 provides control signals which simplify the design of an
external phase locked loop, and write precompensation circuitry. The FDC simplifies and handles
most of the burdens associated with implementing a Floppy Disk Interface.
Hand-shaking signals are provided in the J,tPD765 which make DMA operation easy to incorporate
with the aid of an external DMA Controller chip, such as the J,tPD8257. The FDC will operate in
either DMA or Non·DMA mode. In the Non·DMA mode, the FDC generates interrupts to the
processor every time a data byte is available. In the DMA mode, the processor need only load the
command into the FDC and all data transfers occur under control of theJ,tPD765 and DMA
controller.
There are 15 separate commands which the J,tPD765 will execute. Each of these commands requ ire
multiple 8·bit bytes to fully specify the operation which the processor wishes the FDC to perform.
The following commands are available:
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify
Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense Int"rrupt Status
Sense Drive Status
Address mark detection circuitry is internal to the FDC which simplifies the phase locked loop ana
read electronics. The track stepping rate, head load time, and head unload time may be programmed
by the user. The J,tPD765 offers many additional features such as multiple .ector transfers in both
read and write with a single command, and full IBM compatibility in both single and double
density modes.
o IBM Compatible in Both Single and Double Density Recording Formats
o Programmable Data Record Lengths: 128,256,512, or 1024 Bytes/Sector
o Multi·Sector and Multi-Track Transfer Capability
o Drive Up to 4 Floppy Disks
o Data Scan Capability - Will Scan a Single Sector or an Entire Cylinder's Worth of Data Fields,
Comparing on a Byte by Byte Basis, Data in the Processor's Memory with Data Read from the
Diskette
• Data Transfers in DMA or Non-DMA Mode
o Parallel Seek Operations on Up to Four Drives
o Compatible with Most Microprocessors Including 8080A, 8085A, J,tPD780 (Z80TM)
o Single Phase 8 MHz Clock
o Single +5 Volt Power Supply
o Available in 40 Pin Plastic Dual-in-Line Package
RESET 1
40 vcc
RD 2
FiW/SEEK
WR LCT/DIR
Cs 4
AO 5
FR/STP
HDL
DBO 6
ROY
OB, 7
WP/TS
DB2
DB3
8
9
/oIPD
FLT/TR(
'PSo
DB4 10 765
DB5 11
DB6 12
DB7 13
14
15
16
17 VCO
18 RO
19 ROW
= ______-'WCK
Rev/2
423
1 page  
TIMING WAVEFORMS
PROCESSOR READ OPERATION
: J (AO. Cs. i5AcK
~'"___
TAR__ 1_
--' I--TRA
RD~TRR_t
L..----I
DATA ------I -10TRD}:
I
- l t--TDF
!)I ------
INT _ _ _ _ _ _ _ _ _ _~_T_R"I-"-"-".\-lI
\...
PROCESSOR WRITE OPERATION
pPD765
ClK
DRaJ:
;-
DMA OPERATION
r -\.~_---,r
TAM--J 14-
1
\ TMCY
WR OR RD
I' TMR~-J.:
t-- --ll--TMW IWR)--l~
TMR lAD)
FDD WRITE OPERATION
WRITE CLOCK I
II I
1
11-1 I--TF ~TCy---I
TR~:~~_ _ _~I~I_ _ _ _ _ _ _ _ _~
~WRITE ENABLE
:I
'-
x::_ I It-I-Tcp
PRESHIFTO OR ~~,.....--..t,T¥"I':=1:-~--"'X...- - - -
WRITE DATA
_ I I..oi-TCD --I
II
NORMAL
LATE
EARLY
INVALID
PRESHIFT a
a
a
1
1
PRESHIFT 1
a
1
a
1
II
427
5 Page 
p,PD765
PROCESSOR I NTE RFACE
During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. After each byte of data read or written to Data Register, CPU should
wait for 12 J.i.s b~fore reading MSR. Bits D6 and D7 in the Main Status Register must
be in a a and 1 state, respectively, before each byte of the command word may be
written into the J.i.PD765. Many of the commands require mUltiple bytes, and as a
result the Main Status Register must be read prior to each byte transfer to the J.i.PD765.
On the other hand, during the Result Phase, D6 and D7 in the Main Status Register
must both be 1's (D6 = 1 and D7 = 1) before reading each byte from the Data Register.
Note, this reading of the Main Status Register before each byte transfer to the pPD765
is required in only the Command and Result Phases, and NOT during the Execution
Phase.
During the Execution Phase, the Main Status Register need not be read. If the J.i.PD765
is in the NON-DMA Mode, then the receipt of each data byte (if J.i.PD765 is reading
data from FDD) is indicated by an Interrupt signal on pin 18 (INT = 1). The generation
of a Read signal (RD = 0) or Write signal (WR = 0) will reset the Interrupt as well as
output the Data onto the Data Bus. If the processor cannot handle Interrupts fast
enough (every 13 J.i.s) for MFM and 27 J.i.s for FM mode, then it may poll the Main
Status Register and then bit D7 (ROM) functions just like the Interrupt signal. If a
Write Command is in process then the WR signal performs the reset to the Interrupt
signal.
If the pPD765 is in the DMA Mode, no Interrupts are generated during the Execution
Phase. The J.i.PD765 generates DRO's (DMA Requests) when each byte of data is avail-
aable. The DMA Controller responds to this request with both a DACK = (DMA
Acknowledge) and a FlD = a (Read signal). When the DMA Acknowledge signal goes
low (DACK = 0) then the DMA Request is reset (DRO = 0). If a Write Command has
been programmed then a WR signal will appear instead of RD. After the Execution
Phase has been completed (Terminal Count has occurred) or EaT sector was read/
written, then an Interrupt will occur (INT = 1). This signifies the beginning of the
Result Phase. When the first byte of data is read during the Result Phase, the Interrupt
is automatically reset (I NT = 0).
It is important to note that during the Result Phase all bytes shown in the Command
Table must be read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes must be read in order to successfully complete the
Read Data Command. The J.i.PD765 will not accept a new command until all seven
bytes have been read. Other commands may require fewer bytes to be read during the
Result Phase.
POLLING FEATURE OF
THE pPD765
The J.i.PD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STO, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only after
completing a command. The particular command which has been executed determines
how many of the Status Registers will be read.
The bytes of data which are sent to the J.i.PD765 to form the Command Phase, and are
read out of the J.i.PD765 in the Result Phase, must occur in the order shown in the
II
Command Table. That is, the Command Code must be sent first and the other bytes
•
sent in the prescribed sequence. No foreshortening of the Command or Result Phases
are allowed. After the last byte of data in the Command Phase is sent to the pPD765,
the Execution Phase automatically starts. In a similar fashion, when the last byte of
data is read out in the Result Phase, the command is automatically ended and the
J.i.PD765 is ready for a new command.
usaAfter the Specify command has been sent to the J.i.PD765, the Unit Select line and
US1 will automatically go into a polling mode. In between commands (and between
step pulses in the SEEK command) the J.i.PD765 polls all four FDD's looking for a
change in the Ready line from any of the drives. If the Ready line changes state (usually
due to a door opening or closing) then the J.i.PD765 will generate an interrupt. When
Status Register a (STO) is read (after Sense Interrupt Status is issued), Not Ready (N R)
will be indicated. The polling of the Ready line by the J.i.PD765 occurs continuously
between commands, thus notifying the processor which drives are on or off line. Each
drive is polled every 1.024 ms except during the ReadlWrite commands.
433
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet UPD765.PDF ] | |
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