PDF FT601Q Data sheet ( Hoja de datos )

Número de pieza	FT601Q
Descripción	USB 3.0 to FIFO interface bridge chip
Fabricantes	FTDI
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No Preview Available ! FT600Q-FT601Q IC DatasheetDatasheet Version 1.04 Document No.: FT_001118 Clearance No.: FTDI#424 Future Technology Devices International Ltd. FT600Q-FT601Q IC Datasheet (USB 3.0 to FIFO Bridge) The FT600/FT601 is a USB 3.0 to FIFO interface bridge chip with the following advanced features:  Supports USB 3.0 Super Speed (5Gbps)/USB 2.0 High Speed (480Mbps)/USB 2.0 Full Speed (12Mbps) transfer.      Supported USB Transfer Type:  Control/Bulk/Interrupt   Up to 8 configurable endpoints (PIPEs).   Supports 2 parallel slave FIFO bus protocols 245 and FIFO mode, FT601 with 32 bit parallel interface has a data bursting rate up  to 400MB/s.   Supports 4 IN channels and 4 OUT channels  on FIFO bus connectivity.  Built-in 16kB FIFO data buffer RAM. Supports Remote Wakeup capability. Supports multi voltage I/O: 1.8V, 2.5V and 3.3V. Configurable GPIO support. Internal LDO 1.0V regulator. Integrated power-on-reset circuit. User programmable USB descriptors. Supports Battery Charging spec. BC1.2 battery charging detection. Available as FT600-16bit/FT601-32bit FIFO interface. Industrial operating temperature range: -40 to 85⁰C. Available in compact Pb-free QFN-76(32bit) and QFN- 56(16bit) packages (both RoHS compliant). Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this produ ct. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited 1 1 page FT600Q-FT601Q IC DatasheetDatasheet Version 1.04 Document No.: FT_001118 Clearance No.: FTDI#424 9 Contact Information .................................................... 30 Appendix A – References ................................................... 31 Document References ...................................................................... 31 Acronyms and Abbreviations............................................................ 31 Appendix B – List of Figures and Tables............................. 32 List of Figures .................................................................................. 32 List of Tables.................................................................................... 32 Appendix C – Revision History ........................................... 33 Copyright © Future Technology Devices International Limited 5 5 Page FT600Q-FT601Q IC DatasheetDatasheet Version 1.04 Document No.: FT_001118 Clearance No.: FTDI#424 4 Function Description FT60x is a high performance USB 3.0-to-FIFO interface bridge chip. This device can be used in those applications which require high data throughput such as imaging devices and Multi-Channel FIFO ADC or DAC devices etc. The FIFO interface can support multi-voltage I/O (1.8V, 2.5V, 3.3V) and operating frequencies of 66.67MHz or 100MHz. 100MHz only for 2.5V and 3.3V. There are 2 different proprietary synchronous bus protocols supported; one FIFO bus protocol is called the “Multi-Channel FIFO” bus protocol and the other is the “245 Synchronous FIFO” bus protocol. The latter being an extension of the interface introduced in the FT232H/FT2232H devices. 4.1 Key Features and Function Description Functional Integration. The following features are integral to the IC design: FIFO protocol management, USB 3.0 controller, USB3.0 and USB2.0 PHYs, GPIOs, power management, clock generation, power-on-reset (POR) and LDO regulator. USB 3.0 Protocol Controller. The USB 3.0 Protocol Controller manages the data stream from the device USB control endpoint. It handles the USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO in accordance with the USB 3.0 specification. FIFO Management. This unit is used to manage all PIPE data or buffers in the FIFO memory; the data is sent or received through the FIFO protocol layer. Through this block the FIFO memory can be allocated to each PIPE with any size of memory as long as the total memory allocated to all PIPEs does not exceed the maximum FIFO memory size which is 16KB. Additionally, the FIFO signals have a configurable high drive strength capability and can be set to 18Ω, 25Ω, 35Ω and 50Ω. Multi-Channel FIFO Bus protocol. The multi-Channel FIFO bus is a slave bus and is designed to handle Multi-Channel FIFO connectivity. The bus protocol supports a total of 8 channels (4 INs and 4 OUTs). CLK is the clock output to the FIFO bus master. 245 Synchronous FIFO Bus protocol. The 245 Synchronous FIFO bus is a slave bus with one IN and one OUT FIFO channel supported by this bus protocol. CLK is the clock output to the FIFO bus master. FIFO Bus Clock Option. The device provides the following FIFO bus clock frequency option: 100MHz. FIFO RX/TX Buffer (16k bytes). Data sent from the USB host controller to the FIFO via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents of the FIFO using the RD# pin. (RX relative to the USB interface). Copyright © Future Technology Devices International Limited 11 11 Page

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