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PDF AK4492 Data sheet ( Hoja de datos )
| Número de pieza | AK4492 | |
| Descripción | Quality Oriented 32-Bit 2ch DAC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK4492]
AK4492
Quality Oriented 32-Bit 2ch DAC
1. General Description
The AK4492 is a new generation Premium 32-bit 2ch DAC with VELVET SOUNDTM technology,
achieving industry’s leading level low distortion characteristics. The OSR-Doubler technology establishes
low power consumption and low distortion characteristics. Moreover, the AK4492 has six types of 32-bit
digital filters, realizing simple and flexible sound tuning in wide range of applications. The AK4492
accepts up to 768kHz PCM data and 11.2MHz DSD data, ideal for a high-resolution audio source
playback that are becoming widespread in smartphone, portable audio player etc.
Application: Smart Cellular Phones, IC-Recorders, Bluetooth Headphones, CD/SACD Players, Network
Audios, USB DACs, USB Headphones, Sound Plates/Bars, HD Audio/Voice Conference
Systems, AV Receivers
2. Features
THD+N: -115 dB
DR, S/N: 127 dB (2 Vrms Output)
128 Times Over Sampling
Sampling Rate: 8kHz 768 kHz
32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD=6.0/fs,
Ripple: 0.005dB, Attenuation: 100dB
- Short Delay Slow Roll-off, GD=5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low-dispersion Short Delay Filter
- Super Slow Roll-off
High Tolerance to Clock Jitter
Low Distortion Differential Output
2.8 MHz, 5.6 MHz, 11.2 MHz DSD Input Support
- Filter1 (fc = 39 kHz, 2.8 MHz mode)
- Filter2 (fc = 76 kHz, 2.8 MHz mode)
Digital De-emphasis for 32, 44.1and 48kHz sampling
Soft Mute
Digital Attenuator (255 levels and 0.5dB step + mute)
Mono Mode
External Digital Filter Interface
Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I2S, DSD, TDM
Master Clock
8 kHz ~ 32 kHz: 256 fs or 384 fs or 512 fs or 768 fs or 1024 fs or 1152 fs
8 kHz ~ 54 kHz: 256 fs or 384 fs or 512 fs or 768 fs
8 kHz ~ 108 kHz: 256 fs or 384 fs
108 kHz ~ 216 kHz: 128 fs or 192 fs
~384 kHz: 32 fs or 48 fs or 64 fs or 96 fs
~768 kHz: 16 fs or 32 fs or 48 fs or 64 fs
3-wire, I2C-bus Interface
016011073-E-00
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1 page  
4. Block Diagram
[AK4492]
LDOE
PDN
BICK/BCK/DCLK
SDATA/DINL/DSDL
LRCK/DINR/DSDR
TDMO
LDO
PCM
Data
Interface
TVDD DVDD DVSS AVDD
SSLOW/WCK
TDM0/DCLK
DEM0/DSDL
GAIN/DSDR
External
DF
Interface
DSD
Data
Interface
DATT
Soft Mute
Normal path
DSDD bit “0”
DSD
Filter
Volume bypass
DSDD bit “1”
AVSS
De-emphasis
&
Interpolator
Modulator
SMUTE/CSN
SD/ CCLK/SCL
SLOW/CDTI/SDA
Control
Register
Clock
Divider
PSN
DIF0/ DIF1/ DIF2/ TDM1DCHAIN INVR ACKS/ TESTE HLOAD
DZFL DZFR CAD0
CAD1
/I2C
MCLK
SCF
VSSL
VDDL
AOUTLN
AOUTLP
VCML
VREFHL
Vref VREFLL
VREFLR
VREFHR
VCMR
SCF
MCLK Stop
Detection
Oscillator
IREF
AOUTRP
AOUTRN
VDDR
VSSR
EXTR
Figure 1. Block Diagram
016011073-E-00
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5 Page 
[AK4492]
6. Absolute Maximum Ratings
(AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0 V; Note 5)
Parameter
Symbol
Min.
Max.
Power
Supplies:
Digital I/O
Digital Core
Clock Ineterface
Analog
|AVSS DVSS|
(Note 6)
TVDDam
DVDDam
AVDDam
VDDL/Ram
GND
0.3
0.3
0.3
0.3
-
6.0
2.5
6.0
6.0
0.3
Input Current, Any Pin Except Supplies
IIN -
10
Digital Input Voltage (Note 7)
VIND
0.3 (TVDD+0.3) or 6.0
Ambient Temperature (Power supplied)
Ta 40
85
Storage Temperature
Tstg 65
150
Note 5. All voltages with respect to ground.
Note 6. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
Note 7. Max value of VIND is lower either of (TVDD + 0.3) or 6.0V.
Unit
V
V
V
V
V
mA
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0 V; Note 5)
Parameter
Symbol
Min.
Typ.
Max. Unit
■ LDOE pin = “L”
Digital I/O
TVDD
DVDD 1.8 3.6 V
Clock Ineterface
AVDD
DVDD
1.8 3.6 V
Digital Core
DVDD
1.7 1.8 1.98 V
Power Supplies
Analog
■ LDOE pin = “H”
VDDL/R
4.75
5.0 5.25 V
Digital I/O
TVDD
3.0 3.3 3.6 V
Clock Ineterface
AVDD
3.0 3.3 3.6 V
Analog
VDDL/R
4.75
5.0 5.25 V
Voltage Reference “H” voltage reference VREFHL/R VDDL/R-0.5 - VDDL/R V
(Note 8)
“L” voltage reference VREFLL/R
-
VSSL/R
-
V
Note 5. All voltages with respect to ground.
Note 8. The analog output voltage scales with the voltage of (VREFHL/R VREFLL/R).
Note 9. TVDD and AVDD must be connected to the same ground plane and powered up at the same time.
When not using the LDO (LDOE pin = “L”), all power supplies (DVDD (1.8V), TVDD and AVDD
(3.3V) and VDDL/R (5V)) should be powered up at the same time or sequentially in the order of
3.3V (TVDD, AVDD), 1.8V (DVDD) and 5V (VDDL/R).
Note 10. The internal LDO outputs DVDD (1.8V) when the LDOE pin = “H”. 3.3V (TVDD and AVDD)
power supplies must be powered up before or at the same time with 5V (VDDL/R) power
supplies when the LDOE pin = “H”.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
016011073-E-00
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2016/12
11 Page | ||
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| PDF Descargar | [ Datasheet AK4492.PDF ] | |
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