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PDF AK4673 Data sheet ( Hoja de datos )

Número de pieza AK4673
Descripción Stereo CODEC
Fabricantes AKM 
Logotipo AKM Logotipo



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[AK4673]
AK4673
Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
GENERAL DESCRIPTION
The AK4673 is a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Touch
Screen Controller (TSC) which includes the SAR type ADC. The AK4673 features analog mixing circuits,
PLL and a 4-wire resistive touch screen I/F that allows easy interfacing in mobile phone and portable A/V
player designs. The AK4673 is available in a 57pin BGA package, utilizing less board space than
competitive offerings.
FEATURES
1. Recording Function
4 Stereo Input Selectors
Stereo Mic Input (Full-differential or Single-ended)
Stereo Line Input
MIC Amplifier (+32dB/+26dB/+20dB or 0dB)
Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
ADC Performance: S/(N+D): 83dB DR, S/N: 86dB (MIC-Amp=+20dB)
S/(N+D): 88dB DR, S/N: 95dB (MIC-Amp=0dB)
Wind-noise Reduction Filter
Stereo Separation Emphasis
Programmable EQ
2. Playback Function
Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
Bass Boost
Soft Mute
Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
Stereo Separation Emphasis
Programmable EQ
Stereo Line Output
- Performance: S/(N+D): 88dB, S/N: 92dB
Stereo Headphone-Amp
- S/(N+D): [email protected], S/N: 90dB
- Output Power: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V)
- Pop Noise Free at Power ON/OFF
Analog Mixing: 4 Stereo Input
3. Power Management
4. Master Clock:
(1) PLL Mode
Frequencies:
- MCKI pin: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz,
19.2MHz, 24MHz, 26MHz, 27MHz
- LRCK pin: 1fs
- BICK pin: 32fs or 64fs
(2) External Clock Mode
Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
MS0670-E-00
-1-
2007/09

1 page




AK4673 pdf
[AK4673]
PIN/FUNCTION
No. Pin Name
A1 NC
C2 MPWR
A2 VCOM
B1 VSS1
C1 AVDD
E2 VCOC
RIN3
F2 NC
D2 I2CA
G2 PDN
H1 CADA
H2 SCLA
J1 NC
J2 SDAA
H3 SDTI
J3 SDTO
H4 LRCK
J4 BICK
H5 NC
J6 DVDD
H7 NC
H6 TVDD2
J7 TVDD1
J8 NC
H9 MCKI
G8 NC
G9 NC
H8 MCKO
J9 NC
D8 VSS2
D9 HVDD
C8 HPR
C9 HPL
B8 NC
B9 MUTET
I/O Function
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
O MIC Power Supply Pin
O
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
- Ground 1 Pin
- Analog Power Supply Pin, 2.6 ~ 3.6V
O
Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available.)
This pin should be connected to VSS1 with one resistor and capacitor in series.
I Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available.)
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
I I2C Control Mode Pin. This pin should be tied to AVDD.
Power-Down Mode Pin (This pin is valid only for the Audio Block)
I
“H”: Power-up, “L”: Power-down
This pin does not apply to a power down and a reset for the TSC block and TSC related
registers. Power-down on the TSC block is determined by the PD0 bit shown in Table 61.
I Audio Block I2C bus Slave Address (CADA) bit Select Pin
I Audio Block Control Data Clock Pin.
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
I/O Audio Block Control Data Input Pin.
I Audio Serial Data Input Pin
O Audio Serial Data Output Pin
I/O Input / Output Channel Clock Pin
I/O Audio Serial Data Clock Pin
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
- Digital Power Supply Pin, 2.6 ~ 3.6V
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
- Digital I/O Power Supply Pin (Audio Stream), 1.6 ~ 3.6V
-
Digital I/O Power Supply Pin (uP I/F), 2.5 ~ 3.6V
This pin should be connected to TSVDD pin.
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
I External Master Clock Input Pin
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
O Master Clock Output Pin
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
- Ground 2 Pin
- Headphone Amp Power Supply Pin, 2.6 ~ 5.25V
O Rch Headphone-Amp Output Pin
O Lch Headphone-Amp Output Pin
-
No Connection pin
No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin).
O
Mute Time Constant Control Pin
Connected to VSS2 pin with a capacitor for mute time constant.
MS0670-E-00
-5-
2007/09

5 Page





AK4673 arduino
[AK4673]
Parameter
min typ
max Units
Headphone-Amp Characteristics: DAC HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB, VBAT bit = “0”;
unless otherwise specified.
Output Voltage (Note 15)
HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω
HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW)
S/(N+D)
1.58
2.40
-
-
1.98
3.00
1.0
1.06
2.38 Vpp
3.60 Vpp
- Vrms
- Vrms
HPG bit = “0”, 3dBFS, HVDD=3.3V, RL=22.8Ω
HPG bit = “1”, 3dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW)
S/N (A-weighted)
(Note 16)
(Note 17)
60
-
-
-
80
-
70
80
20
70
90
90
- dBFS
- dBFS
- dBFS
- dBFS
- dB
- dB
Interchannel Isolation
(Note 16)
(Note 17)
65
-
75
80
- dB
- dB
Interchannel Gain Mismatch
(Note 16)
(Note 17)
-
-
0.1
0.1
0.8 dB
0.8 dB
Load Resistance
16 -
-Ω
Load Capacitance
C1 in Figure 2
C2 in Figure 2
-
-
- 30 pF
- 300 pF
Note 15. Output voltage is proportional to AVDD voltage.
Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.
Note 16. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω.
Note 17. HPG bit = “1”, HVDD=5V, RL=100Ω.
HP-Amp
HPL/HPR pin
Measurement Point
47μF
6.8Ω
C1 0.22μF
10Ω
C2 16Ω
Figure 2. Headphone-Amp output circuit
MS0670-E-00
- 11 -
2007/09

11 Page







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