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PDF AK4629 Data sheet ( Hoja de datos )
| Número de pieza | AK4629 | |
| Descripción | High Performance Multi-channel Audio CODEC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK4629]
AK4629
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION
The AK4629 is a single chip audio CODEC that includes four ADC channels and eight DAC channels.
The converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit
architecture for the DAC, enabling very low noise performance. The AK4629 ADC supports both
single-ended and differential inputs and outputs. A wide range of applications can be realized, including
home theater, pro audio and car audio. The AK4629 is available in a 48-pin LQFP package.
FEATURES
4ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-ended / Differential Input
- S/(N+D): 92dB (Single-ended, Differential)
- Dynamic Range, S/N: 102dB (Single-ended), 103dB (Differential)
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
8ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
High Jitter Tolerance
TTL Level Digital I/F
3-wire Serial and I2C Bus µP I/F for mode setting
Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
128fs for fs=120kHz to 192kHz
Power Supply: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
Small 48pin LQFP
MS1277-E-02
-1-
2012/03
1 page  
[AK4629]
No. Pin Name
I/O Function
31 VCOM
O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
32 VREFH
I Positive Voltage Reference Input Pin, AVDD
33 AVDD
- Analog Power Supply Pin, 4.5V∼5.5V
34 VSS2
- Analog Ground Pin, 0V
35 DZF1
O Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when PS pin is “H”.
36 DZF2
O Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when PS pin is “H”.
37 RIN2-
I ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
38 RIN2+
I ADC2 Rch Analog Positive Input Pin (SGL pin = “L”)
RIN2
I ADC2 Rch Analog Input Pin (SGL pin = “H”)
39 LIN2-
I ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
40 LIN2+
ADC2 Lch Analog Positive Input Pin (SGL pin = “L”)
LIN2
I ADC2 Lch Analog Input Pin (SGL pin = “H”)
41 RIN1-
I ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
42
RIN1+
RIN1
I ADC1 Rch Analog Positive Input Pin (SGL pin = “L”)
I ADC1 Rch Analog Input Pin (SGL pin = “H”)
43 LIN1-
I ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
44 LIN1+
I ADC1 Lch Analog Positive Input Pin (SGL pin = “L”)
LIN1
I ADC1 Lch Analog Input Pin (SGL pin = “H”)
45 TST1
I Test Pin
This pin should be connected to VSS1.
46 SGL
I Single-ended Input Mode Select Pin.
“L”: ADC Differential Input Mode
“H”: ADC Single-ended Input Mode
47 DZFE
I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
48 SMUTE
I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
Note 1. SMUTE and DFS0 pins are ORed with register data when the PS pin= “L”.
Note 2. The output pin (DZF1 and DZF2) of zero detection results of each lineout channels can be selected by DZFM3-0
bits when the PS pin and DZFE pin= “L”. (Table 11)
Note 3. All digital input pins except for pull-down should not be left floating.
MS1277-E-02
-5-
2012/03
5 Page 
[AK4629]
Parameter
Symbol
min
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
tCSS
tCSH
50
50
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 19)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR -
Fall Time of Both SDA and SCL Lines
tF -
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb -
Power-down & Reset Timing
PDN Pulse Width
(Note 20)
tPD
150
PDN “↑” to SDTO1-2 valid
(Note 21)
tPDV
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK4629 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 21. These cycles are the number of LRCK rising from the PDN pin rising edge.
Note 22. I2C-bus is a trademark of NXP B.V.
typ
522
max Unit
ns
ns
ns
ns
ns
ns
ns
ns
400 kHz
- μs
- μs
- μs
- μs
- μs
- μs
- μs
1.0 μs
0.3 μs
- μs
50 ns
400 pF
ns
1/fs
MS1277-E-02
- 11 -
2012/03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4629.PDF ] | |
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