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PDF AK7755 Data sheet ( Hoja de datos )
| Número de pieza | AK7755 | |
| Descripción | DSP | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK7755]
AK7755
DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp
1. General Description
The AK7755 is a highly integrated digital signal processor, including a mono ADC, a stereo audio CODEC, a
MIC pre-amplifier, a line-out amplifier and digital audio I/F. The audio DSP has 2560step at fs = 48kHz
parallel processing power. As the AK7755 is a RAM based DSP, it is programmable for user requirements
such as high performance hands free function and acoustic effects. The AK7755 is available in a space saving
small 36-pin QFN package.
2. Features
DSP
- Word length: 24-bit (Data RAM 24-bit floating point)
- Instruction cycle: 8.1ns (2560fs at fs=48kHz)
- Multiplier 24 x 24 → 48-bit (double precision available)
- Divider 20 / 20 → 20-bit (with floating point normalization function)
- ALU: 52-bit arithmetic operation (with overflow margin 4-bit)
- Program RAM: 4096 × 36-bit
- Coefficient RAM: 2048 × 24-bit
- Data RAM: 2048 × 24-bit (24-bit floating point)
- Offset Register: 32 × 13-bit
- Delay RAM: 8192 × 24-bit
- Accelerator Coefficient RAM: 2048 × 20-bit
- Accelerator Data RAM: 2048 × 16-bit
- JX pins (Interrupt)
- Master/Slave Operation
- Master Clock: 2560fs
(Internally Generated by PLL from 32, 48, 64, 128, 256 and 384fs clock)
Two Digital Interfaces (I/F1, I/F2)
- Digital Signal Input Port (4ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Digital Signal Input Port (6ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Short / Long Frame
- 24-bit linear, 8-bit A-law, 8-bit μ-law
- TDM 256fs (8ch) MSB justified and I2S formats
Stereo 24-bit ADC:
- Sampling Frequency: fs=8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 91dB, DR, S/N: 102dB
- Two-Channel Analog Input Selector (Differential, Single-ended Input)
- Channel Independent Mic Analog Gain Amplifier
(0~18dB (2dB Step), 18~36dB (3dB Step))
- Analog DRC (Dynamic Range Control)
- Channel Independent Digital Volume (24~-103dB, 0.5dB Step Mute)
- Digital HPF for DC Offset Cancelling
Mono 24-bit ADC
- Sampling Frequency: 8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 90dB; DR, S/N: 100dB
- Line Amplifier: 21dB ~ -21dB, 3dB Step
- Digital Volume (24dB ~ -103dB, 0.5dB step, Mute)
- Digital HPF for DC Offset Cancelling
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■ DSP Block Diagram
[AK7755]
Pointer
CP0, CP1
DP0, DP1
DLP0, DLP1
Coefficient RAM
2048w×24-Bit
Data RAM
Delay RAM
2048w x 24-Bit(20.4f) 8192w x 24-Bit(20.4f)
CBUS(24-Bit)
DBUS(28-Bit)
OFREG
32w x 13-Bit
MPX24
MPX24
XY
Multiply
24 ×24 → 48-Bit
48-Bit
28-Bit
52-Bit
MUL DBUS
SHIFT
48-Bit
AB
ALU
52-Bit
Overflow Margin: 4-Bit
52-Bit
DR0 3
52-Bit
Over Flow Data
Generator
Micon I/F
Control
Serial I/F
DEC
PRAM
4096w×36-Bit
PC
Stack : 5level(max)
TMP 12×24-Bit
PTMP(LIFO) 6×24-Bit
2×16/20/24-Bit DIN4
2×16/20/24-Bit DIN3
2×16/20/24-Bit DIN2
2×16/20/24-Bit DIN1
2×16/20/24-Bit
2×16/20/24-Bit
2×16/20/24-Bit
2×16/20/24-Bit
DOUT4
DOUT3
DOUT2
DOUT1
Accelerator
Coefficient RAM
(ACCRAM)
2048w x 20-Bit
Data RAM
(ACDRAM)
2048w x 16-Bit
Division 2020→20 Peak Detector
Figure 2. DSP Block Diagram
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[AK7755]
6. Absolute Maximum Ratings
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies
Analog
Digital1(I/F)
Digital2(Core)
DVSS-AVSS (Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 3)
Digital Input Voltage (Note 4)
AVDD
TVDD
DVDD
ΔGND
IIN
VINA
VIND
-0.3 4.3
-0.3 4.3
-0.3 1.6
-0.3 0.3
－ ±10
-0.3 (AVDD+0.3)≤4.3
-0.3 (TVDD+0.3)≤4.3
Ambient Temperature
Ta -40
85
Storage Temperature
Tstg -65
150
Note 2. All voltages with respect to ground. AVSS and DVSS must be the same voltage.
Note 3. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 4. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V.
Unit
V
V
V
V
mA
V
V
℃
℃
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol min typ max Unit
Power Supplies
Analog
AVDD 3.0 3.3 3.6
V
Digital1(I/F)
TVDD 1.7 3.3 3.6
V
Digital2(Core)
DVDD 1.14 1.2
1.3
V
Note 5. AVDD and TVDD must be powered up first before DVDD when DVDD is supplied externally
(LDOE pin = “L”). In this case, the power-up sequence between AVDD and TVDD is not critical.
When using the internal regulator (LDOE pin = “H”), the power-up sequence between AVDD and
TVDD is not critical. But all power supplies must be ON before starting operation of the AK7755
by PDN pin = “H”.
Note 6. Do not turn off the power supply of the AK7755 with the power supply of the surrounding device
turned on. Pull-up of SDA and SCL pins must not exceed TVDD.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK7755.PDF ] | |
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