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PDF IDT70T3719M Data sheet ( Hoja de datos )
| Número de pieza | IDT70T3719M | |
| Descripción | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
IDT70T3719/99M
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆ High-speed data access
– Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ Selectable Pipelined or Flow-Through output mode
◆ Counter enable and repeat features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Interrupt and Collision Detection Flags
◆ Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆ 2.5V (±100mV) power supply for core
◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆ Industrial temperature range (-40°C to +85°C) is
available at 133MHz
◆ Available in a 324-pin Green Ball Grid Array (BGA)
◆ Includes JTAG Functionality
◆ Green parts available, see ordering information
Functional Block Diagram
BE7L
BE7R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0h 1h
h
1h 0h
h
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
FT/PIPEL
1
0
1/0
1h 0h
0/1
a
1a 0a
h
Byte 0
I/O0L - I/O71L
CLKL
A17L(1)
A 0L
REPEATL
ADSL
CN TENL
Byte 7
Counter/
Address
Reg.
B
BB
B
W
WW
W
0
77
0
L
LR
R
D OUT0-8_ L
D OUT9-17 _L
DO UT18-26_L
D OUT 27-3 5_ L
D OUT 36-4 4_L
D OUT 45-5 3_L
D OUT 54-6 2_L
D OUT 63-7 2_L
D OUT0-8_ R
D OUT9-17 _R
D OU T1 8-2 6_ R
DOUT27 -35_ R
DOUT36 -4 4_ R
DOUT45 -5 3_ R
DOUT54 -6 2_ R
DOUT63 -7 2_ R
256/128K x 72
MEM ORY
ARRAY
DIN_L
DIN_R
ADDR_L
ADDR_R
0a 1a
h
0h 1h
a
0/1
Byte 7
Counter/
Address
Reg.
Byte 0
I/O0R - I/O71R
A17R(1)
CLKR
A 0R
REPE ATR
AD SR
CNTENR
COL L
INTL
CE0L
CE1L
R/WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0R
CE1R
R/WR
COL R
INTR
NOTES:
ZZ
(2)
L
ZZ
CONTROL
LOGIC
ZZ
(2)
R
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2014 Integrated Device Technology, Inc.
TDI
T DO
C E0 R
1 CE1R
0
1/0
OER
FT/PIPER
,
,
JTAG
TC K
TMS
TRST
5687 drw 01
JULY 2014
DSC 5687/3
1 page  
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control (1,2,3,4,5)
OE CLK CE0 CE1 Byte Enables
R/W ZZ I/O Operation(6)
MODE
X H X All BE = X
X L All Bytes= High-Z
Deselected: Power Down
XX
L All BE = X
X L All Bytes = High-Z
Deselected: Power Down
X L H All BE = H
X L All Bytes = High-Z
All Bytes Deselected
X
L
H BEn = L, All other BE = H
L
L Byten = DIN, All other Bytes = High-Z Write to Byte X Only
X L H BE4-7 = L, BE0-3 = H
L
L Byte4-7 = DIN, Byte0-3 = High-Z
Write to Lower Bytes Only
X L H BE4-7 = H, BE0-3 = L
L
L Byte4-7 = High-Z, Byte0-3 = DIN
Write to Upper Bytes Only
X L H BE0-7 = L
L L Byte0-7 = DIN
Write to All Bytes
L
L
H BEn = L, All other BE = H
H
L Byten = DOUT, All other Bytes = High-Z Read Byte X Only
L L H BE4-7 = L, BE0-3 = H
H
L Byte4-7 = DOUT, Byte0-3 = High-Z
Read Lower Bytes Only
L L H BE4-7 = H, BE0-3 = L
H
L Byte4-7 = High-Z, Byte0-3 = DOUT
Read Upper Bytes Only
L L H All BE = L
H L All Bytes = DOUT
Read All Bytes
H X X X All BE = X
X L All Bytes = High-Z
Outputs Disabled
X X X X All BE = X
X H All Bytes = High-Z
Sleep Mode
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5. For the examples shown here, BEn may correspond to any of the eight byte enable signals.
5687 tbl 03
Truth Table II—Address Counter Control (1,2)
Previous Internal
Internal Address
Address Address Used
CLK
ADS(4)
CNTEN REPEAT(4,6)
I/O(3)
MODE
An X
An
L
X
H DI/O(n) External Address Used
X An An + 1 H L(5) H DI/O(n+1) Counter Enabled-Internal Address generation
X
An + 1 An + 1
H
H
H DI/O(n+1) Enabled Address Blocked-Counter disabled (An + 1 reused)
X X An X X
L DI/O(n) Counter Set to last valid ADS load
NOTES:
5687 tbl 04
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.452
5 Page 
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCH2
tCYC2
tCL2
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
DATAOUT
(1)
OE
tSW tHW
tSA tHA
An
An + 1
(1 Latency)
tCD2
tCKLZ (1)
An + 2
tDC
Qn
An + 3
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
tOE
,
5687 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSC tHC
(3)
tSB tHB
R/W
ADDRESS(4)
DATAOUT
tSW tHW
tSA tHA
An
tCD1
tCKLZ
An + 1
tDC
Qn
An + 2
Qn + 1
tOHZ
An + 3
tCKHZ
Qn + 2(5)
tOLZ
tDC
OE (1)
NOTES:
tOE
5687 drw 06
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
,
6.1412
11 Page | ||
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| PDF Descargar | [ Datasheet IDT70T3719M.PDF ] | |
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