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PDF ADE7761B Data sheet ( Hoja de datos )
| Número de pieza | ADE7761B | |
| Descripción | Energy Metering IC | |
| Fabricantes | Analog Devices | |
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Energy Metering IC with On-Chip Fault and
Missing Neutral Detection
ADE7761B
FEATURES
GENERAL DESCRIPTION
High accuracy, active energy measurement IC supports
IEC 62053-21
Less than 0.1% error over a dynamic range of 1000 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Continuous monitoring of the phase and neutral current
allows fault detection in 2-wire distribution systems
Current channel input level best suited for shunt and current
transformer sensors
Uses the larger of the two currents (phase or neutral) to bill,
even during a fault condition
Continuous monitoring of the voltage and current inputs
allows missing neutral detection
Uses one current input (phase or neutral) to bill when
missing neutral is detected
Two logic outputs (FAULT and REVP) can be used to indicate
a potential miswiring, fault, or missing neutral condition
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time
Reference 2.5 V ± 8% (drift 30 ppm/°C typical) with external
overdrive capability
Single 5 V supply, low power
The ADE7761B is a high accuracy, fault-tolerant, electrical energy
measurement IC intended for use with 2-wire distribution systems.
The part specifications surpass the accuracy requirements as
quoted in the IEC 62053-21 standard. The only analog circuitry
used on the ADE7761B is in the ADCs and reference circuit.
All other signal processing (such as multiplication and filtering)
is carried out in the digital domain. This approach provides
superior stability and accuracy over extremes in environmental
conditions and over time. The ADE7761B incorporates a fault
detection scheme similar to the ADE7751 by continuously
monitoring both phase and neutral currents. A fault is indicated
when the currents differ by more than 6.25%.
The ADE7761B incorporates a missing neutral detection scheme
by continuously monitoring the input voltage. When a missing
neutral condition is detected (no voltage input), the ADE7761B
continues billing based on the active current signal (see the
Missing Neutral Mode section). The missing neutral condition
is indicated when the FAULT pin goes high. The ADE7761B
supplies average active power information on the low frequency
outputs, F1 and F2. The CF logic output gives instantaneous
active power information.
The ADE7761B includes a power supply monitoring circuit on
the VDD supply pin. Internal phase matching circuitry ensures
that the voltage and current channels are matched. An internal
no-load threshold ensures that the ADE7761B does not exhibit
any creep when there is no load.
PGA AGND
13 8
FUNCTIONAL BLOCK DIAGRAM
FAULT
15
VDD
1
V1A 2
V1N 4
V1B 3
MISCAL 7
ADC
ADC
ADC
A>B
HPF
B>A
A≠B
ZERO-CROSSING
DETECTION
MISSING NEUTRAL
GAIN ADJUST
POWER
SUPPLY MONITOR
ADE7761B
SIGNAL PROCESSING
BLOCK
LPF
V2P 6
V2N 5
ADC
2.5V
3kΩ
REFERENCE
INTERNAL
OSCILLATOR
MISSING NEUTRAL
DETECTION
DIGITAL-TO-FREQUENCY CONVERTER
9
REFIN/OUT
14
RCLKIN
17
DGND
Figure 1.
10 11 12 16 18 19 20
SCF S1 S0 REVP CF F2 F1
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
ADE7761B
Parameter
LOGIC INPUTS5
PGA, SCF, S1, and S0
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS5
CF, REVP, and FAULT
Output High Voltage, VOH
Output Low Voltage, VOH
F1 and F2
Output High Voltage, VOH
Output Low Voltage, VOH
POWER SUPPLY
VDD
IDD
Value Unit
2.4 V, min
0.8 V, max
±3 μA, max
10 pF, max
4 V, min
1 V, max
4 V, min
1 V, max
4.75 V, min
5.25 V, max
3.65 mA, max
Test Conditions/Comments
VDD = 5 V ± 5%
VDD = 5 V ± 5%
Typical 10 nA, VIN = 0 V to VDD
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VDD = 5 V ± 5%, ISOURCE = 10 mA
VDD = 5 V ± 5%, ISINK = 10 mA
For specified performance
5 V − 5%
5 V + 5%
1 See plots in the Typical Performance Characteristics section.
2 See the Terminology section for explanation of specifications.
3 See the Fault Detection section for explanation of fault detection functionality.
4 See the Missing Neutral Detection section for explanation of missing neutral detection functionality.
5 Sample tested during initial release and after any redesign or process change that might affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = −40°C to +85°C. Sample tested during
initial release and after any redesign or process change that might affect this parameter. See Figure 2.
Table 2.
Parameter
t1 1
t2
t3
t41
t5
t6
Value
120
See Table 8
1/2 t2
90
See Table 8
CLKIN/4
Unit Test Conditions/Comments
ms F1 and F2 pulse width (logic high)
sec Output pulse period (see the Transfer Function section)
sec Time between F1 falling edge and F2 falling edge
ms CF pulse width (logic high)
sec CF pulse period (see the Transfer Function section)
sec Minimum time between F1 pulse and F2 pulse
1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.
Timing Diagram
t1
F1
t6 t2
F2 t3
t4 t5
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. 0 | Page 4 of 24
5 Page 
ADE7761B
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7761B is defined by
Percentage Error =
⎜⎛
⎜⎝
Energy Registered by ADE7761B
True Energy
− True Energy
⎟⎞
⎟⎠
×
100%
Phase Error Between Channels
The high-pass filter (HPF) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response among channels, a phase correction network is
also placed in the current channel. The phase correction network
ensures a phase match between the current channels and the
voltage channels to within ±0.1° over a range of 45 Hz to
65 Hz and ±0.2° over a range of 40 Hz to 1 kHz.
Power Supply Rejection (PSR)
PSR quantifies the ADE7761B measurement error as a percentage
of reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (5 V) is taken.
A second reading is obtained with the same input signal levels
when an ac signal (175 mV rms/100 Hz) is introduced onto the
supplies. Any error introduced by this ac signal is expressed as
a percentage of reading (see the Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies (5 V)
is taken. A second reading is obtained with the same input signal
levels when the power supplies are varied ±5%. Any error
introduced is again expressed as a percentage of reading.
ADC Offset Error
This is the dc offset associated with the analog inputs to the ADCs.
With the analog inputs connected to AGND, the ADCs still see
a dc analog input signal. The magnitude of the offset depends on
the input gain and range selection (see the Typical Performance
Characteristics section). However, when HPFs are switched on,
the offset is removed from the current channels and the power
calculation is not affected by this offset.
Gain Error
The gain error in the ADE7761B ADCs is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. It is measured with a gain of 1 in
Channel V1A. The difference is expressed as a percentage of the
ideal frequency, which is obtained from the transfer function
(see the Transfer Function section).
Gain Error Match
The gain error match is defined as the gain error (minus the offset)
obtained when switching between a gain of 1 or 16. It is expressed
as a percentage of the output ADC code obtained under a gain of 1.
Rev. 0 | Page 10 of 24
11 Page | ||
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| PDF Descargar | [ Datasheet ADE7761B.PDF ] | |
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