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PDF AD7264 Data sheet ( Hoja de datos )
| Número de pieza | AD7264 | |
| Descripción | Simultaneous Sampling SAR ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
1 MSPS, 14-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
AD7264
FEATURES
Dual, simultaneous sampling, 14-bit, 2-channel ADC
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7264
500 kSPS for AD7264-5
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32
Device offset calibration
System gain calibration
On-chip reference: 2.5 V
−40°C to +105°C operation
High speed serial interface
Compatible with SPI, QSPI™, MICROWIRE™, and DSP
48-lead LFCSP and LQFP packages
GENERAL DESCRIPTION
The AD7264 is a dual, 14-bit, high speed, low power, successive
approximation ADC that operates from a single 5 V power supply
and features throughput rates of up to 1 MSPS per on-chip ADC
(500 kSPS for the AD7264-5). Two complete ADC functions
allow simultaneous sampling and conversion of two channels.
Each ADC is preceded by a true differential analog input with a
PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6,
×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7264 contains four comparators. Comparator A and
Comparator B are optimized for low power, whereas Comparator C
and Comparator D have fast propagation delays. The AD7264
features a calibration function to remove any device offset error
and programmable gain adjust registers to allow input path (for
example, sensor) offset and gain compensation. The AD7264 has
an on-chip 2.5 V reference that can be disabled if an external
reference is preferred. The AD7264 is available in 48-lead LFCSP
and LQFP packages.
The AD7264 is ideally suited for monitoring small amplitude
signals from a variety of sensors. The devices include all the
functionality needed for monitoring the position feedback signals
from a variety of analog encoders used in motor control systems.
FUNCTIONAL BLOCK DIAGRAM
AVCC
VREFA
REF
BUF
AD7264
14-BIT
VA+
VA–
PGA
T/H
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
CONTROL
LOGIC
VB+
VB–
VREFB
CA_CBVCC
CA+
CA–
CB+
CB–
CA_CB_GND
CC_CDVCC
CC+
CC–
CD+
CD–
CC_CD_GND
PGA
14-BIT
T/H
SUCCESSIVE
OUTPUT
APPROXIMATION DRIVERS
ADC
BUF
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
AGND
Figure 1.
DGND
DOUTA
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
VDRIVE
DOUTB
PD0/DIN
PD1
PD2
COUTA
COUTB
COUTC
COUTD
PRODUCT HIGHLIGHTS
1. Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
2. Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC
(500 kSPS for the AD7264-5). The conversion result of
both ADCs is simultaneously available on separate data
lines or in succession on one data line if only one serial
port is available.
3. Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
4. Internal 2.5 V reference.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7264
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
COMPARATORS
Input Offset
Comparator A and Comparator B
Comparator C and Comparator D
Offset Voltage Drift
Input Common-Mode Range3
Input Capacitance3
Input Impedance3
IDD Normal Mode (Static)6
Min Typ Max
0.7 × VDRIVE
4
0.8
±1
VDRIVE − 0.2
0.4
±1
5
Twos complement
19 × tSCLK
400
1
500
±2
±2
0.5
0 to 4
0 to 1.7
4
1
±4
±4
Comparator A and Comparator B
Comparator C and Comparator D
Propagation Delay Time2
3
6 8.5
60
120 170
High to Low, tPHL
Comparator A and Comparator B
Comparator C and Comparator D
Low to High, tPLH
Comparator A and Comparator B
Comparator C and Comparator D
Delay Matching
1.4 3.5
0.95
0.20 0.32
0.13
24
0.93
0.18 0.28
0.12
Comparator A and Comparator B
Comparator C and Comparator D
±250
±10
Data Sheet
Unit
V
V
μA
pF
V
V
μA
pF
Test Conditions/Comments
VIN = 0 V or VDRIVE
ns
ns
MSPS
kSPS
AD7264
AD7264-5
mV
mV
μV/°C
V
V
pF
GΩ
μA
μA
μA
μA
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
TA = 25°C to 105°C only
All comparators
CA_CBVCC = 5 V
CA_CBVCC = 2.7 V
25 pF load, COUTx = 0 V, VCM = AVCC/2,
VOVERDRIVE = 200 mV differential
CA_CBVCC = 3.3 V
CA_CBVCC = 5.25 V
CC_CDVCC = 3.3 V
CC_CDVCC = 5.25 V
VCM = AVCC/2, VOVERDRIVE = 200 mV
differential
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
VCM = AVCC/2, VOVERDRIVE = 200 mV
differential
Rev. C | Page 4 of 29
5 Page 
AD7264
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000
4000
6000
8000
AVCC = 5V
VfSD=RIV1EMS=P5SV
TA = 25°C
INTERNAL REFERENCE
GAIN = 2
10,000 12,000 14,000 16,000
CODE
Figure 5. Typical DNL at Gain of 2
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
AVCC = 5V
VfSD=RIV1EMS=P5SV
TA = 25°C
INTERNAL REFERENCE
GAIN = 2
2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
Figure 6. Typical INL at Gain of 2
0
AVCC = 5V
–20 fVSD=RIV1EMS=P2S.7V
TfIAN
=
=
25°C
100kHz
–40 INTERNAL REFERENCE
SNR = 79dB
THD = –96dB
–60 GAIN = 2
–80
–100
–120
–140
0
50 100 150 200 250 300 350 400 450
FREQUENCY (kHz)
Figure 7. Typical FFT at Gain of 2
Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
AVCC = 5V TA = 25°C
fVSD=RIV1EMS=P5SV
INTERNAL REFERENCE
GAIN = 32
–1.0
0 2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
Figure 8. Typical DNL at Gain of 32
2.0
–1.5
–1.0
–0.5
AVCC = 5V
fVSD=RIV1EMS=P5SV
TA = 25°C
INTERNAL REFERENCE
GAIN = 32
0
–0.5
–1.0
–1.5
–2.0
0
2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
Figure 9. Typical INL at Gain of 32
0
AVCC = 5V
–20 VfSD=RIV1EMS=P2S.7V
TfIAN
=
=
25°C
100kHz
–40 INTERNAL REFERENCE
SNR = 72dB
THD = –87dB
–60 GAIN = 32
–80
–100
–120
–140
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
Figure 10. Typical FFT at Gain of 32
Rev. C | Page 10 of 29
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7264.PDF ] | |
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