PDF ADRF6720 Data sheet ( Hoja de datos )

Número de pieza	ADRF6720
Descripción	Wideband Quadrature Modulator
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs ADRF6720 FEATURES GENERAL DESCRIPTION I/Q modulator with integrated fractional-N PLL The ADRF6720 is a wideband quadrature modulator with an RF output frequency range: 700 MHz to 3000 MHz integrated synthesizer ideally suited for 3G and 4G Internal LO frequency range: 356.25 MHz to 2855 MHz communication systems. The ADRF6720 consists of a high Output P1dB: 12.2 dBm at 2140 MHz linearity broadband modulator, an integrated fractional-N Output IP3: 32.6 dBm at 2140 MHz phase-locked loop (PLL), and four low phase noise multicore Carrier feedthrough: −40.3 dBm at 2140 MHz voltage controlled oscillators (VCOs). Sideband suppression: −37.6 dBc at 2140 MHz Noise floor: −157.9 dBm/Hz at 2140 MHz Baseband 1 dB modulation bandwidth: >1000 MHz Baseband input bias level: 0.5 V Power supply: 3.3 V/425 mA Integrated RF tunable balun allowing single-ended RF output Multicore integrated VCOs HD3/IP3 optimization Sideband suppression and carrier feedthrough optimization High-side/low-side LO injection Programmable via 3-wire serial port interface (SPI) The ADRF6720 local oscillator (LO) signal can be generated internally via the on-chip integer-N and fractional-N synthesizers, or externally via a high frequency, low phase noise LO signal. The internal integrated synthesizer enables LO coverage from 356.25 MHz to 2855 MHz using the multicore VCOs. In the case of internal LO generation or external LO input, quadrature signals are generated with a divide-by-2 phase splitter. When the ADRF6720 is operated with an external 1 × LO input, a polyphase filter generates the quadrature inputs to the mixer. 40-lead 6 mm × 6 mm LFCSP The ADRF6720 offers digital programmability for carrier APPLICATIONS 2G/3G/4G/LTE broadband communication systems Microwave point-to-point radios Satellite modems Military/aerospace Instrumentation feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The ADRF6720 is fabricated using an advanced silicon- germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP package with an exposed pad. Performance is specified over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM VPOSx I+ 3 I– 4 40 35 30 V TO I LO NULLING DAC 26 22 17 11 PHASE CORRECTION 6 ADRF6720 27 ENBL 24 RFOUT Q– 8 Q+ 9 REFIN 39 CP 36 VTUNE 32 LO NULLING DAC V TO I PLL QUAD DIVIDER LOIN– 33 LOIN+ 34 POLYPHASE FILTER 2 5 7 10 16 20 23 25 29 37 38 GND PHASE CORRECTION 18 LOOUT+ 19 LOOUT– Figure 1. LDO 2.5V LDO VCO 12 28 DECL1 DECL2 SERIAL PORT INTERFACE 31 DECL3 15 CS 14 SCLK 13 SDIO Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADRF6720 Data Sheet Parameter Output IP2 Output IP3 Noise Floor RF OUTPUT = 2300 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RF OUTPUT = 2600 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor SYNTHESIZER SPECIFICATIONS Figure of Merit (FOM)1 REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Amplitude Phase Detector Frequency Test Conditions/Comments f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier offset Baseband VIQ = 1 V p-p differential POUT − P(fLO ± (2 × fBB)) POUT − P(fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier offset Baseband VIQ = 1 V p-p differential POUT − P(fLO ± (2 × fBB)) POUT − P(fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.45 V p-p differential I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier offset Synthesizer specifications referenced to the modulator output REFIN, MUXOUT pins Min 5.7 11.4 Typ Max Unit 57.7 dBm 32.6 dBm −157.9 −156.3 dBm/Hz dBm/Hz 4.6 0.62 11.8 −37.6 −36.6 −1.5 −0.0285 −54.8 −56.6 57.6 30.4 −159.2 −157.5 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm/Hz 3.9 −0.08 11.3 −36.5 −42.3 −0.55 −0.021 −60.3 −54.7 56.6 29.9 −159.2 −157.3 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm/Hz −218.5 dBc/Hz/Hz 320 MHz 4 dBm 40 MHz Rev. 0 \| Page 4 of 44 5 Page ADRF6720 Pin No. 30 31 32 33, 34 35 36 37 38 39 40 Mnemonic VPOS6 DECL3 VTUNE LOIN−, LOIN+ VPOS7 CP GND GND REFIN VPOS8 EP Data Sheet Description 3.3 V Supply Voltage for VCO LDO. Decouple VPOS6 with 100 pF and 0.1 µF capacitors located close to the pin. Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this pin and ground. VCO Tuning Voltage. Differential External LO Inputs. 3.3 V Supply Voltage for Charge Pump. Decouple VPOS7 with 100 pF and 0.1 µF capacitors located close to the pin. Charge Pump Output. Charge Pump Ground. PLL Reference Ground. PLL Reference Input. 3.3 V Supply Voltage for PLL Reference. Decouple VPOS8 with 100 pF and 0.1 µF capacitors located close to the pin. Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. 0 \| Page 10 of 44 11 Page

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