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PDF ADF7021-N Data sheet ( Hoja de datos )
| Número de pieza | ADF7021-N | |
| Descripción | High Performance Narrow-Band Transceiver IC | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Low power, narrow-band transceiver
Frequency bands using dual VCO
80 MHz to 650 MHz
842 MHz to 916 MHz
Programmable IF filter bandwidths of
9 kHz, 13.5 kHz, and 18.5 kHz
Modulation schemes: 2FSK, 3FSK, 4FSK, MSK
Spectral shaping: Gaussian and raised cosine filtering
Data rates supported: 0.05 kbps to 24 kbps
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 63 steps
Automatic power amplifier (PA) ramp control
Receiver sensitivity
−130 dBm at 100 bps, 2FSK
−122 dBm at 1 kbps, 2FSK
On-chip image rejection calibration
High Performance
Narrow-Band Transceiver IC
ADF7021-N
On-chip VCO and fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC)
Digital received signal strength indication (RSSI)
Integrated Tx/Rx switch
0.1 µA leakage current in power-down mode
APPLICATIONS
Narrow-band, short range device (SRD) standards
ARIB STD-T67, ETSI EN 300 220, Korean SRD standard,
FCC Part 15, FCC Part 90, FCC Part 95
Low cost, wireless data transfer
Remote control/security systems
Wireless metering
Wireless medical telemetry service (WMTS)
Home automation
Process and building control
Pagers
RLNA
RSET
FUNCTIONAL BLOCK DIAGRAM
CE CREG(1:4)
TEMP
SENSOR
MUX
7-BIT ADC
LDO(1:4)
MUXOUT
TEST MUX
RFIN
RFINB
LNA
IF FILTER
RSSI/
LOG AMP
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
Tx/Rx
CONTROL
GAIN
PA RAMP
AGC
CONTROL
AFC
CONTROL
SERIAL
PORT
RFOUT
÷1/÷2
VCO1
÷2
DIV P
N/N + 1
Σ-Δ
MODULATOR
VCO2
MUX
CP PFD
DIV R
OSC
2FSK
3FSK
4FSK
MOD CONTROL
CLK
DIV
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
TxRxCLK
TxRxDATA
SWD
SLE
SDATA
SREAD
SCLK
L1 L2 VCOIN CPOUT
OSC1 OSC2
Figure 1.
CLKOUT
Rev. B
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF7021-N
GENERAL DESCRIPTION
The ADF7021-N is a high performance, low power, narrow-
band transceiver based on the ADF7021. The ADF7021-N has
IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz, making
it ideally suited to worldwide narrowband standards and
particularly those that stipulate 12.5 kHz channel separation.
It is designed to operate in the narrow-band, license-free ISM
bands and in the licensed bands with frequency ranges of
80 MHz to 650 MHz and 842 MHz to 916 MHz. The part has
both Gaussian and raised cosine transmit data filtering options
to improve spectral efficiency for narrow-band applications. It
is suitable for circuit applications targeted at the Japanese ARIB
STD-T67, the European ETSI EN 300 220, the Korean short
range device regulations, the Chinese short range device
regulations, and the North American FCC Part 15, Part 90, and
Part 95 regulatory standards. A complete transceiver can be
built using a small number of external discrete components,
making the ADF7021-N very suitable for price-sensitive and
area-sensitive applications.
The range of on-chip FSK modulation and data filtering options
allows users greater flexibility in their choice of modulation
schemes while meeting the tight spectral efficiency requirements.
The ADF7021-N also supports protocols that dynamically switch
among 2FSK, 3FSK, and 4FSK to maximize communication
range and data throughput.
The transmit section contains two voltage controlled oscillators
(VCOs) and a low noise fractional-N PLL with an output
resolution of <1 ppm. The ADF7021-N has a VCO using an
internal LC tank (421 MHz to 458 MHz, 842 MHz to 916 MHz)
and a VCO using an external inductor as part of its tank circuit
(80 MHz to 650 MHz). The dual VCO design allows dual-band
operation where the user can transmit and/or receive at any
frequency supported by the internal inductor VCO and can also
transmit and/or receive at a particular frequency band
supported by the external inductor VCO.
Data Sheet
The frequency-agile PLL allows the ADF7021-N to be used in
frequency-hopping, spread spectrum (FHSS) systems. Both
VCOs operate at twice the fundamental frequency to reduce
spurious emissions and frequency pulling problems.
The transmitter output power is programmable in 63 steps from
−16 dBm to +13 dBm and has an automatic power ramp control
to prevent spectral splatter and help meet regulatory standards.
The transceiver RF frequency, channel spacing, and modulation
are programmable using a simple 3-wire interface. The device
operates with a power supply range of 2.3 V to 3.6 V and can be
powered down when not in use.
A low IF architecture is used in the receiver (100 kHz), which
minimizes power consumption and the external component
count yet avoids dc offset and flicker noise at low frequencies.
The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz,
and 18.5 kHz. The ADF7021-N supports a wide variety of
programmable features including Rx linearity, sensitivity, and
IF bandwidth, allowing the user to trade off receiver sensitivity
and selectivity against current consumption, depending on the
application. The receiver also features an automatic frequency
control (AFC) loop with programmable pull-in range that allows
the PLL to track out the frequency error in the incoming signal.
The receiver achieves an image rejection performance of 56 dB
using an IR calibration scheme that does not require the use of
an external RF source.
An on-chip ADC provides readback of the integrated tempera-
ture sensor, external analog input, battery voltage, and RSSI
signal, which provides savings on an ADC in some applications.
The temperature sensor is accurate to ±10°C over the full
operating temperature range of −40°C to +85°C. This accuracy
can be improved by performing a 1-point calibration at room
temperature and storing the result in memory
Rev. B | Page 4 of 65
5 Page 
ADF7021-N
Data Sheet
DIGITAL SPECIFICATIONS
Table 4.
Parameter
Min Typ
Max Unit Test Conditions/Comments
TIMING INFORMATION
Chip Enabled to Regulator Ready
10
µs CREG (1:4) = 100 nF
Chip Enabled to Tx Mode
32-bit register write time = 50 µs
TCXO Reference
1
ms
XTAL
2 ms
Chip Enabled to Rx Mode
32-bit register write time = 50 µs, IF filter coarse
calibration only
TCXO Reference
1.2 ms
XTAL
2.2 ms
Tx-to-Rx Turnaround Time
390 µs + (5 × tBIT)
Time to synchronized data out, includes AGC
settling (three AGC levels)and CDR synchronization;
see the AGC Information and Timing section for
more details; tBIT = data bit period
LOGIC INPUTS
Input High Voltage, VINH
0.7 × VDD
V
Input Low Voltage, VINL
0.2 × VDD V
Input Current, IINH/IINL
±1 µA
Input Capacitance, CIN
10 pF
Control Clock Input
50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH
DVDD − 0.4
V IOH = 500 µA
Output Low Voltage, VOL
0.4 V IOL = 500 µA
CLKOUT Rise/Fall
5 ns
CLKOUT Load
10 pF
Rev. B | Page 10 of 65
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADF7021-N.PDF ] | |
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