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PDF HMC835LP6GE Data sheet ( Hoja de datos )

Número de pieza HMC835LP6GE
Descripción FRACTIONAL-N PLL
Fabricantes Analog Devices　
Logotipo Analog Devices Logotipo



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HMC835LP6GE
v04.1113
FRACTIONAL-N PLL WITH INTEGRATED VCO
33 - 4100 MHz
Features
Wideband: 33 - 4100 MHz
Maximum Phase Detector Rate: 100 MHz
Low Phase Noise: -110 dBc/Hz in Band @2GHz
PLL FOM:
-230 dBc/Hz Integer Mode, -227 dBc/Hz Fractional
Mode
< 94 fs Integrated RMS Jitter (1 kHz to 100 MHz)
Low Noise Floor: -167 dBc/Hz
2 Differential RF outputs
Typical Applications
• MIMO Radio Architectures
• Cellular Infrastructure
• Cellular backhaul
• Communication Test Equipment
• CATV Equipment
Functional Diagram
External LO Input
Exact Frequency Mode:
0 Hz Fractional Frequency Error
Programmable RF Output Phase
Output Phase Synchronous Frequency Changes
Output Phase Synchronization
RF Output Mute Function
40 Lead 6x6 mm SMT Package: 36 mm2
• Phased Array Applications
• DDS Replacement
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HMC835LP6GE pdf
HMC835LP6GE
v04.1113
FRACTIONAL-N PLL WITH INTEGRATED VCO
33 - 4100 MHz
Electrical Specifications (Continued)
Parameter
Power Supply Voltages
3.3 V Supplies
5 V Supplies
Power Supply Currents
+5V Analog Charge Pump (VDDCP)
+5V VCO core + LO1 Buffer Only (VCC2)
+5V VCO core + LO2 Buffer Only (VCC2)
Condition
AVDD, VCCHF, VCCPS,
3VRVDD,DVDD3V,VCCPD
VCC1,VCC2,VDDLS, VDDCP
Single-Ended Output[4]
Differential Output [4]
Single-Ended Output[4]
Differential Output [4]
+5V VCO core + LO1 Buffer + LO2 Buffer
(VCC2)
Single-Ended Output[4]
Differential Output [4]
+5V VCO Divider and RF/PLL Buffer (VCC1)
Fo/1 Mode
Fo/N (2,4...62) Mode
+3.3V VCCPD, VCCPS, VCCHF, DVDD,
RVDD
Power Down - Crystal Off
Reg 01h=0,
Crystal Not Clocked
(5V and 3.3V combined)
Power Down - Crystal On, 100 MHz
Reg 01h=0,
Crystal Clocked 100 MHz
Power on Reset
Typical Reset Voltage on DVDD
Min DVDD Voltage for No Reset
Power on Reset Delay
VCO Open Loop Phase Noise at fo @ 4 GHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
VCO Open Loop Phase Noise at fo @ 3 GHz/2 = 1.5 GHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
Min.
3.1
4.8
99
104
99
104
108
118
52
1.5
Typ.
3.3
5
6
27
48
1
5
700
250
-78
-108
-134.5
-156
-171
-89
-119
-143.7
-160.7
-167
Max.
Units
3.5 V
5.2 V
110
129
110
129
130 mA
168
73
µA
mA
mV
V
µs
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
[4] Minimum and Maximum current various by different Gain settings from 0 to 3
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HMC835LP6GE arduino
HMC835LP6GE
v04.1113
FRACTIONAL-N PLL WITH INTEGRATED VCO
33 - 4100 MHz
Figure 25. Reference Input Sensitivity,
Sinusoidal Wave [17]
-200
Figure 26. Phase Adjust at 0 degree[18]
1000
-205
-210
500
-215
-220
0
-225
-230
-500
-235
-20
-15 -10
-5
REFERENCE POWER (dBm)
0
5
14 MHz sin
50 MHz sin
25 MHz sin
100 MHz sin
Figure 27. Phase Adjust at 90 degree [19]
-1000
-500
-400
-300
-200 -100
0
TIME(ps)
100 200 300
Figure 28. Phase Adjust at 180 degree [20]
1000
1000
500 500
00
-500
-500
-1000
-600
-400
-200
TIME(ps)
0
200
-1000
-600
-400
-200
TIME(ps)
0
200
Figure 29. Figure of Merit
-200
-210
-220
FOM 1/f Noise
-230
Typ FOM vs Offset
FOM Floor
-240
102
103 104
OFFSET (Hz)
105
106
Figure 30. RF Output Return Loss Diff [21]
0
-5
-10
Return Loss (LO DIFFERENTIAL OUTPOUT)
-15
-20
-25
-30
100
1000
OUTPUT FREQUENCY (MHz)
[18] Loop Filter #1 from Table 1 used. Phase adjust feature limited to Fundamental Mode operation (2050 to 4100MHz). The plot is capture by using
two identical HMC835LP6GE eval boards driven by the same 10MHz external reference source from instrument via on board HMC1031MS8E to
generate a 50 MHz reference frequency to lock with HMC835LP6GE, and captured with 26GHz 50 Ω high speed Oscilloscope. Seed value in Reg1A
for both HMC835LP6GE initially set to 0. Then Reg1A was adjusted in HMC835LP6GE #1 to bring the phase into alignment with HMC835LP6GE #2.
[19] Phase adjust feature limited to Fundamental Mode operation (2050 to 4100MHz). Starting condition as stated in [18] then HMC835LP6GE #2 seed
value Reg 1Ah set to 400000h. Required seed value calculated from (Phase Adjust (degrees)/360˚ x 224.
[20] Phase adjust feature limited to Fundamental Mode operation (2050 to 4100MHz). Starting condition as stated in [18] then HMC835LP6GE #2
seed value Reg 1Ah set to 800000h.
[21] Both LO1 and LO2 Output Buffer Enabled in Reg 17h[5:4] as 11.Differential or single-ended mode programmed in Reg 17h[9:8].
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