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PDF ADRF5130 Data sheet ( Hoja de datos )
| Número de pieza | ADRF5130 | |
| Descripción | Reflective Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
High Power, 44 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 3.5 GHz
ADRF5130
FEATURES
Reflective, 50 Ω design
Low insertion loss: 0.6 dB typical to 2.0 GHz
High isolation: 50 dB typical to 2.0 GHz
High power handling
RF input power, continuous wave (CW) at TCASE = 85°C
43 dBm maximum operating
46.5 dBm absolute maximum rating
High linearity
0.1 dB compression (P0.1dB): 46 dBm typical
Input third-order intercept (IP3): 68 dBm typical to 2 GHz
ESD ratings
Human body model (HBM): 2 kV, Class 2
Charged device model (CDM): 1.25 kV
Single positive supply: VDD = 5 V
Positive control, TTL-compatible: VCTL = 0 V or VDD
24-lead, 4 mm × 4 mm LFCSP package (16 mm2)
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
GENERAL DESCRIPTION
The ADRF5130 is a high power, reflective, 0.7 GHz to 3.5 GHz,
silicon, single-pole, double-throw (SPDT) switch in a leadless,
surface-mount package. The switch is ideal for high power and
cellular infrastructure applications, like long-term evolution (LTE)
base stations. The ADRF5130 has high power handling of 43 dBm
(maximum), a low insertion loss of 0.6 dB, input third-order
intercept of 68 dBm (typical), and 0.1 dB compression (P0.1dB)
FUNCTIONAL BLOCK DIAGRAM
VCTL
ADRF5130
RF1 RF2
RFC
Figure 1.
of 46 dBm. On-chip circuitry operates at a single, positive
supply voltage of 5 V and typical supply current of 1.06 mA,
making the ADRF5130 an ideal alternative to pin diode-based
switches.
The device comes in a RoHS compliant, compact, 24-lead, 4 mm ×
4 mm LFCSP package.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADRF5130
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Bias Voltage Range (VDD)
Control Voltage Range (VCTL)
RF Input Power,1 Continuous Wave
Channel Temperature
Storage Temperature Range
Operating Temperature Range
Peak Reflow Temperature (MSL3)2
Thermal Resistance (Channel to Package
Bottom)
Electrostatic Discharge (ESD) Sensitivity
HBM
CDM
Rating
−0.3 V to +5.5 V
−0.3 V to +5.5 V
46.5 dBm
135°C
−65°C to +150°C
−40°C to +105°C
260°C
17°C/W
2 kV (Class 2)
1.25 kV
1 For the recommended operating conditions, see Table 1.
2 See the Ordering Guide section.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 4 of 10
5 Page 
ADRF5130
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.90
0.85
0.80
SEATING
PLANE
4.10
4.00 SQ
3.90
TOP VIEW
0.50
BSC
0.30
0.25
0.18
19
18
24
1
EXPOSED
PAD
DETAIL A
(JEDEC 95)
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
2.85
2.70 SQ
2.55
13 6
0.50
0.40
12 7
BOTTOM VIEW
0.20 MIN
0.30
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
Figure 15. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
ADRF5130BCPZ
−40°C to +105°C
ADRF5130BCPZ-R7 −40°C to +105°C
ADRF5130-EVALZ
−40°C to +105°C
1 Z = RoHS-Compliant Part.
2 See the Absolute Maximum Ratings section.
MSL Rating2
MSL3
MSL3
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Data Sheet
Package Option
CP-24-16
CP-24-16
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14081-0-1/17(A)
Rev. A | Page 10 of 10
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ADRF5130.PDF ] | |
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