DataSheet.es    


PDF ADRF5020 Data sheet ( Hoja de datos )

Número de pieza ADRF5020
Descripción Silicon SPDT Switch
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



Hay una vista previa y un enlace de descarga de ADRF5020 (archivo pdf) en la parte inferior de esta página.


Total 13 Páginas

No Preview Available ! ADRF5020 Hoja de datos, Descripción, Manual

Data Sheet
FEATURES
Ultrawideband frequency range: 100 MHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.0 dB to 30 GHz
High isolation: 60 dB to 30 GHz
High input linearity
1 dB power compression (P1dB): 28 dBm typical
Third-order intercept (IP3): 52 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
ESD sensitivity: Class 1, 1 kV human body model (HBM)
20-terminal, 3 mm × 3 mm, land grid array package
No low frequency spurious
Radio frequency (RF) settling time (to 0.1 dB of final RF
output): 15 ns
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The ADRF5020 is a general-purpose, single-pole, double-throw
(SPDT) switch manufactured using a silicon process. It comes
in a 3 mm × 3 mm, 20-terminal land grid array (LGA) package
and provides high isolation and low insertion loss from 100 MHz
to 30 GHz.
100 MHz to 30 GHz,
Silicon SPDT Switch
ADRF5020
FUNCTIONAL BLOCK DIAGRAM
RF2
ADRF5020
RFC
50Ω
50Ω
VSS
EN
CTRL
VDD
RF1
Figure 1.
This broadband switch requires dual supply voltages, +3.3 V
and −2.5 V, and provides CMOS/LVTTL logic-compatible
control.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADRF5020 pdf
ADRF5020
Parameter
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive
Negative
Digital Control Voltage
RF Input Power2
Through Path
Terminated Path
Hot Switching
Case Temperature
Symbol Test Conditions/Comments
VDD
VSS
VCTL
PIN f = 600 MHz to 30 GHz, TCASE = 85°C
RF signal is applied to RFC or through
connected RF1/RF2
RF signal is applied to terminated RF1/RF2
RF signal is present at RFC while switching
between RF1 and RF2
TCASE
1 For input linearity performance at frequencies less than 600 MHz, see Figure 15 to Figure 17.
2 For power derating at frequencies less than 600 MHz, see Figure 2 to Figure 4.
Data Sheet
Min Typ Max Unit
3.0
−2.75
0
−40
5.4
−2.25
VDD
24
24
18
+85
V
V
V
dBm
dBm
dBm
°C
Rev. A | Page 4 of 12

5 Page





ADRF5020 arduino
ADRF5020
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 18 and Figure 19 show the top and cross sectional views
of the evaluation board, which uses 4-layer construction with a
copper thickness of 0.5 oz (0.7 mil) and dielectric materials
between each copper layer.
EDGE PLATING 5 × 520mil
R 32mil
570mil
Data Sheet
Figure 20 shows the actual ADRF5020 evaluation board with
component placement. Two power supply ports are connected
to the VDD and VSS test points, TP5 and TP2, and the ground
reference is connected to the GND test point, TP1. On each
supply trace, a 100 pF bypass capacitor is used, and unpopulated
components positions are available for applying extra bypass
capacitors.
40mil
40mil
1500mil
Figure 18. Evaluation Board Layout (Top View)
0.5oz Cu (0.7mil)
G = 5mil
W = 14mil
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
T = 0.7mil
RO4003
0.5oz Cu (0.7mil)
H = 8mil
FR4
0.5oz Cu (0.7mil)
FR4
0.5oz Cu (0.7mil)
Figure 19. Evaluation Board (Cross Sectional View)
All RF and dc traces are routed on the top copper layer whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. Top dielectric
material is 8 mil Rogers RO4003, offering good high frequency
performance. The middle and bottom dielectric materials are
FR-4 type materials to achieve an overall board thickness of 62 mil.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model with a width of 14 mil and ground
spacing of 5 mil to have a characteristic impedance of 50 Ω. For
good RF and thermal grounding, as many plated through vias
as possible are arranged around transmission lines and under
the exposed pad of the package.
Figure 20. Populated Evaluation Board
Two control ports are connected to the EN and CTRL test
points, TP3 and TP4. On each control trace, a resistor position
is available to improve the isolation between the RF and control
signals. The RF ports are connected to the RFC, RF1, and RF2
connectors (J1, J2, and J3) that are end launch 2.4 mm RF
connectors. A through transmission line that connects
unpopulated RF connectors (J7 and J8) is also available to
measure the loss of the PCB. Figure 21 and Table 5 are the
evaluation board schematic and bill of materials, respectively.
The evaluation board shown in Figure 20 is available from
Analog Devices, Inc., upon request.
Rev. A | Page 10 of 12

11 Page







PáginasTotal 13 Páginas
PDF Descargar[ Datasheet ADRF5020.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ADRF5020Silicon SPDT SwitchAnalog Devices
Analog Devices
ADRF5021Silicon SPDT SwitchAnalog Devices
Analog Devices

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar