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PDF AD9530 Data sheet ( Hoja de datos )
| Número de pieza | AD9530 | |
| Descripción | Low Jitter Clock Generator | |
| Fabricantes | Analog Devices | |
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Data Sheet
4 CML Output, Low Jitter Clock Generator
with an Integrated 5.4 GHz VCO
AD9530
FEATURES
Fully integrated, ultralow noise phase-locked loop (PLL)
4 differential, 2.7 GHz common-mode logic (CML) outputs
2 differential reference inputs with programmable internal
termination options
<232 fs rms absolute jitter (12 kHz to 20 MHz) with a non-
ideal reference and 8 kHz loop bandwidth
<100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz
loop bandwidth and low jitter input reference clock
Supports low loop bandwidths for jitter attenuation
Manual switchover
Single 2.5 V typical supply voltage
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
40 Gbps/100 Gbps optical transport network (OTN) line side
clocking
Clocking of high speed analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs)
Data communications
GENERAL DESCRIPTION
The AD9530 is a fully integrated PLL and distribution supporting,
clock cleanup, and frequency translation device for 40 Gbps/
100 Gbps OTN applications. The internal PLL can lock to one
of two reference frequencies to generate four discrete output
frequencies up to 2.7 GHz.
The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow
noise voltage controlled oscillator (VCO). All four outputs are
individually divided down from the internal VCO using two high
speed VCO dividers (the Mx dividers) and four individual 8-bit
channel dividers (the Dx dividers). The high speed VCO dividers
offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of
possible output frequencies. The AD9530 is configurable for
loop bandwidths <15 kHz to attenuate reference noise.
The AD9530 is available in a 48-lead LFCSP and operates from a
single 2.5 V typical supply voltage.
The AD9530 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
AD9530
REFA
REFA
REFB
REFB
800MHz MAX
R DIVIDER
(1 TO 255)
PLL
SERIAL PORT AND
CONTROL LOGIC
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
D1 DIVIDER
(1 TO 255)
D2 DIVIDER
(1 TO 255)
D3 DIVIDER
(1 TO 255)
D4 DIVIDER
(1 TO 255)
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
SDIO SDO SCLK CS
LD
Figure 1.
CML 50Ω SOURCE TERMINATED
2.7GHz MAX
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9530
Data Sheet
SPECIFICATIONS
Typical values are given for VDD = 2.5 V ± 5%, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD
range and TA (−40°C to +85°C) variations listed in Table 1.
SUPPLY VOLTAGE AND TEMPERATURE RANGE SPECIFICATIONS
Table 1.
Parameter
SUPPLY VOLTAGE
TEMPERATURE
Ambient Temperature Range
Junction Temperature1
Symbol Min Typ Max Unit Test Conditions/Comments
VDD
2.375 2.5 2.625 V
2.5 V ± 5%
TA −40 +25 +85 °C
TJ 115 °C
1 The is the maximum junction temperature for which device performance is guaranteed. Note that the Absolute Maximum Ratings section may have a higher
maximum junction temperature, but device operation or performance is not guaranteed above the number that appears here. To calculate the junction temperature,
see the Power Dissipation and Thermal Considerations section.
SUPPLY CURRENT SPECIFICATIONS
Table 2.
Parameter
SUPPLY CURRENT OTHER THAN CLOCK THE
DISTRIBUTION CHANNEL
Typical Operation 1
Reference Input VDD (Pin 3 and Pin 7)
PLL VDD (Pin 12)
Rotary Travelling Wave Oscillator (RTWO) VDD
(Pin 20 to Pin 23)
SUPPLY CURRENT FOR AN INDIVIDUAL CLOCK
DISTRIBUTION CHANNEL
CML
Internal Termination Disabled
800 mV
900 mV
1000 mV
1100 mV
Internal Termination Enabled
800 mV
900 mV
1000 mV
1100 mV
Min Typ Max Unit Test Conditions/Comments
Current listed in the Typ column is at nominal VDD at
25°C; current listed in the Max column is at
maximum VDD and worst case temperature
fRTWO = 5300.16 MHz; VCO mode = low power;
REFA enabled at 110.42 MHz; REFB disabled;
R divider = 1; M1 and M3 divider = 3; M2 divider =
powered down; phase frequency detector (PFD) =
110.42 MHz; OUT1 CML output at 1766.72 MHz;
OUT2, OUT3, and OUT4 outputs and dividers
powered down; single-ended output swing level =
800 mV; outputs terminated externally with 50 Ω
to VDD
8.2 10.7 mA
Combined current of Pin 3 and Pin 7
18.2 24
mA
747 860 mA
Combined current of Pin 20 to Pin 23
Each output channel has a dedicated VDD pin; all
current values are listed for a single driver supply
pin operating at 1766.72 MHz; output terminated
externally, 50 Ω to VDD; these specifications include
the current required for the external load resistors
28.8 35.5 mA
30.7 37.6 mA
32.6 39.8 mA
34.5 41.8 mA
47.6 57.2 mA
51.5 61.5 mA
55.3 65.8 mA
59.0 70.1 mA
Rev. 0 | Page 4 of 41
5 Page 
AD9530
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (HIGH LOOP BANDWIDTH) SPECIFICATIONS
Table 10.
Parameter
CML OUTPUT ABSOLUTE TIME JITTER
Min Typ
93
Max Unit
fs rms
Test Conditions/Comments
REFA enabled and ac-coupled; R divider = 1; Mx divider value = 2; loop
bandwidth = 80 kHz; output divider bypassed; single-ended output
swing level = 1000 mV; no internal termination; VCO in high power
mode; reference frequency = 860 MHz; output frequency = 2.58 GHz;
integration bandwidth = 12 kHz to 20 MHz; absolute jitter value also
depends on the noise of the input clock in the 12 kHz to 80 kHz range
RESET AND REF_SEL PINS SPECIFICATIONS
Table 11.
Parameter
INPUT CHARACTERISTICS
Voltage
Logic 1
Logic 0
Current
Logic 1
Logic 0
Capacitance
RESET TIMING
Pulse Width Low
RESET Inactive to Start of Register Programming
Min
VDD − 0.5
100
50
Typ Max Unit
VDD V
0.5 V
1 µA
36 µA
3 pF
ns
ms
LD PIN SPECIFICATIONS
Table 12.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
Symbol
VOH
VOL
Min Typ Max Unit Test Conditions/Comments
1 mA output load
VDD − 0.5
V
0.5 V
SERIAL CONTROL PORT SPECIFICATIONS
Table 13.
Parameter
CS (INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
SCLK (INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
Symbol Min
VDD − 0.4
VDD − 0.4
Typ Max Unit
V
0.4 V
1 µA
32 µA
3 pF
V
0.4 V
45 µA
1 µA
3 pF
Rev. 0 | Page 10 of 41
Test Conditions/Comments
CS has an internal 75 kΩ pull-up resistor
SCLK has an internal 75 kΩ pull-down resistor
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9530.PDF ] | |
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