|
|
PDF AD9523 Data sheet ( Hoja de datos )
| Número de pieza | AD9523 | |
| Descripción | Jitter Cleaner and Clock Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9523 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
Jitter Cleaner and Clock Generator with
14 Differential or 29 LVCMOS Outputs
AD9523
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC_IN, OSC_IN
PLL1
PLL2
AD9523
OUT0,
OUT0
OUT1,
OUT1
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
ZERO
DELAY
EEPROM
14-CLOCK
DISTRIBUTION
OUT12,
OUT12
OUT13,
OUT13
ZD_IN, ZD_IN
Figure 1.
GENERAL DESCRIPTION
The AD9523 provides a low power, multi-output, clock distribution
function with low jitter performance, along with an on-chip PLL
and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.
The AD9523 is designed to support the clock requirements for long
term evolution (LTE) and multicarrier GSM base station designs.
It relies on an external VCXO to provide the reference jitter cleanup
to achieve the restrictive low phase noise requirements necessary
for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to half the period of the signal coming
out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up and
chip reset.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9523
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control low
power mode off, divider phase = 1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5% and TA = 25°C, unless otherwise noted.
Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
3.3 V 3.3 V ± 5%
VDD3_PLL2, Supply Voltage for PLL2
3.3 V 3.3 V ± 5%
VDD3_REF, Supply Voltage Clock Output Drivers Reference
3.3
V 3.3 V ± 5%
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.3 V 3.3 V ± 5%
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
1.8 V 1.8 V ± 5%
TEMPERATURE
Ambient Temperature Range, TA
−40 +25 +85 °C
Junction Temperature, TJ
115 °C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
37 43
mA Decreases by 9 mA typical if REFB is turned off
VDD3_PLL2, Supply Voltage for PLL2
67 77.7 mA
VDD3_REF, Supply Voltage Clock Output Drivers Reference
LVPECL Mode
56
mA Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
LVDS Mode
4 4.8 mA Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
HSTL Mode
3 3.6 mA Values are independent of the number of
outputs turned on
CMOS Mode
3 3.6 mA Values are independent of the number of
outputs turned on
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2
3.5 4.2 mA Current for each divider: f = 245.76 MHz
CLOCK OUTPUT DRIVERS
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
16 17.4 mA f = 61.44 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
5 6.2 mA f = 245.76 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
17 18.9 mA f = 122.88 MHz
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
21 24.0 mA f = 122.88 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
14 16.3 mA f = 122.88 MHz
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
2 2.4 mA f = 15.36 MHz, 10 pF load
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
2 The current for Pin 63 (VDD1_OUT[0:3]) is 2× that of the other VDD11.8_OUT[x:y] pairs.
Rev. D | Page 4 of 60
5 Page 
AD9523
Data Sheet
Parameter
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
Min
Typ Max
Unit Test Conditions/Comments
2.7 V
0.4 V
25 MHz
8 ns
12 ns
3.3 ns
0 ns
14 ns
10 ns
0 ns
6 ns
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 16.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSPIKE
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with
a Bus Capacitance from 10 pF to 400 pF
TIMING
Min Typ
0.7 × VDD
−10
0.015 × VDD
20 + 0.1 CB1
Max Unit
0.3 × VDD
+10
V
V
µA
V
50 ns
0.4 V
250 ns
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start
Condition, tIDLE
Setup Time for a Repeated Start Condition, tSET;
STR
Hold Time (Repeated) Start Condition, tHLD;STR
1.3
0.6
0.6
400 kHz
µs
µs
µs
Setup Time for Stop Condition, tSET;STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
SCL, SDA Fall Time, tFALL
Data Setup Time, tSET;DAT
Data Hold Time, tHLD;DAT
0.6
1.3
0.6
20 + 0.1 CB1
20 + 0.1 CB1
100
100
µs
µs
µs
300 ns
300 ns
ns
880 ns
Capacitive Load for Each Bus Line, CB1
400 pF
Test Conditions/Comments
Note that all I2C timing values are referred to
VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)
After this period, the first clock pulse is
generated
This is a minor deviation from the original I²C
specification of 0 ns minimum2
1 CB is the capacitance of one bus line in picofarads (pF).
2 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
Rev. D | Page 10 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9523.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9520-0 | 12 LVPECL/24 CMOS Output Clock Generator | Analog Devices |
| AD9520-1 | 12 LVPECL/24 CMOS Output Clock Generator | Analog Devices |
| AD9520-2 | 12 LVPECL/24 CMOS Output Clock Generator | Analog Devices |
| AD9520-3 | 12 LVPECL/24 CMOS Output Clock Generator | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |