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PDF ADF4153A Data sheet ( Hoja de datos )
| Número de pieza | ADF4153A | |
| Descripción | Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Fractional-N Frequency Synthesizer
ADF4153A
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4153A
REFIN
MUXOUT
×2
DOUBLER
4-BIT
R COUNTER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
THIRD ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
–
REFERENCE
CHARGE
PUMP
CURRENT
SETTING
CP
RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. A
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4153A
Data Sheet
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLK
t4 t5
DATA
DB23 (MSB)
LE
t1
LE
t2 t3
DB22
DB2
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. A | Page 4 of 24
5 Page 
ADF4153A
Data Sheet
REGISTER MAPS
9-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
N DIVIDER REG (R0)
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
FL1 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F6 F5 F4 F3 F2 F1 C2 (0) C1 (0)
MUXOUT
4-BIT
R COUNTER
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
R DIVIDER REG (R1)
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P3 M3 M2 M1 0 P1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C2 (0) C1 (1)
CONTROL REG (R2)
RESYNC
CP CURRENT
SETTING
CONTROL
BITS
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
S4 S3 S2 S1 U6 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0)
NOISE AND SPUR
MODE
NOISE AND SPUR REG (R3)
RESERVED
CONTROL
BITS
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 T8 T7 T6 T5 0 0 0 T1 C2 (1) C1 (1)
Figure 16. Register Summary
Rev. A | Page 10 of 24
11 Page | ||
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