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Analog Devices - 6 GHz PLL Frequency Synthesizer

Numéro de référence ADF4196
Description 6 GHz PLL Frequency Synthesizer
Fabricant Analog Devices 
Logo Analog Devices 





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ADF4196 fiche technique
Data Sheet
Low Phase Noise, Fast Settling, 6 GHz
PLL Frequency Synthesizer
ADF4196
FEATURES
Fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
within 20 μs
1 degree rms phase error at 4 GHz RF output
Digitally programmable output phase
RF input range up to 6 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Pulse Doppler radar
Instrumentation and test equipment
Beam-forming/phased array systems
GENERAL DESCRIPTION
The ADF4196 frequency synthesizer can be used to implement
local oscillators (LO) in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time require-
ments for base stations, and the fast settling feature makes the
ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency
detector (PFD) and a precision differential charge pump.
A differential amplifier converts the differential charge pump
output to a single-ended voltage for the external voltage controlled
oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter-
polator, working with the N divider, allows programmable modulus
fractional-N division. Additionally, the 4-bit reference (R) counter
and on-chip frequency doubler allow selectable reference signal
(REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a VCO. The
switching architecture ensures that the PLL settles within the
GSM time slot guard period, removing the need for a second
PLL and associated isolation switches. This decreases the cost,
complexity, PCB area, shielding, and characterization found on
previous ping-pong GSM PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
SDVDD DVDD1 DVDD2 DVDD3 AVDD
VP1 VP2 VP3
RSET
REFIN
MUXOUT
CLK
DATA
LE
×2
DOUBLER
HIGH-Z
OUTPUT
MUX
24-BIT
DATA
REGISTER
4-BIT R
COUNTER
/2
DIVIDER
VDD
DGND
LOCK DETECT
RDIV
NDIV
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE +
PUMP
DIFFERENTIAL
AMPLIFIER
+
N COUNTER
FRACTION MODULUS
REG
REG
INTEGER
REG
ADF4196
SW1
CPOUT+
CPOUT–
SW2
CMR
AIN–
AIN+
AOUT
SW3
RFIN+
RFIN–
AGND1
AGND2
DGND1
DGND2
Figure 1.
DGND3 SDGND SWGND
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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