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PDF HMC8400 Data sheet ( Hoja de datos )

Número de pieza HMC8400
Descripción GaAs pHEMT MMIC Low Noise Amplifier
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
2 GHz to 30 GHz, GaAs
pHEMT MMIC Low Noise Amplifier
HMC8400
FEATURES
Output power for 1 dB compression (P1dB): 14.5 dBm typical
Saturated output power (PSAT): 17 dBm typical
Gain: 13.5 dB typical
Noise figure: 2 dB
Output third-order intercept (IP3): 26.5 dBm typical
Supply voltage: 5 V at 67 mA
50 Ω matched input/output
Die size: 2.7 mm × 1.35 mm × 0.05 mm
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
GENERAL DESCRIPTION
The HMC8400 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC). The HMC8400 is a wideband low
noise amplifier that operates between 2 GHz and 30 GHz. The
amplifier provides 13.5 dB of gain, a 2 dB noise figure, 26.5 dBm
output IP3, and 14.5 dBm of output power at 1 dB gain compres-
sion, requiring 67 mA from a 5 V supply. The HMC8400 is self
biased with only a single positive supply needed to achieve a
drain current IDD of 67 mA. The HMC8400 also has a gain control
option, VGG2. The HMC8400 amplifier input/outputs are internally
matched to 50 Ω and dc blocked, facilitating integration into
multichip modules (MCMs). All data is taken with the chip
connected via two 0.025 mm (1 mil) wire bonds of minimal
length 0.31 mm (12 mils).
3
VDD
2 VGG2
1
RFIN
FUNCTIONAL BLOCK DIAGRAM
HMC8400
4
RFOUT
Figure 1.
Rev. A
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Tel: 781.329.4700
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Technical Support
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1 page




HMC8400 pdf
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Drain Bias Voltage (VDD)
Second Gate Bias Voltage (VGG2)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 17.2 mW/°C Above 85°C)
Thermal Resistance, θJA (Channel to
Bottom Die)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
Rating
8V
−2.5 V to +3 V
23 dBm
175°C
1.55 W
58°C/W
−65°C to +150°C
−55°C to +85°C
250 V (Class 1A)
HMC8400
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 14

5 Page





HMC8400 arduino
Data Sheet
THEORY OF OPERATION
The HMC8400 is a GaAs, pHEMT, MMIC low noise amplifier.
The basic architecture is that of a self biased cascode distributed
amplifier with an integrated RF choke for the drain. The cascode
distributed architecture uses a fundamental cell consisting of a
stack of two field effect transistors (FETs) connected from source to
drain. The fundamental cell is then duplicated several times, with
transmission lines interconnecting the drains of the top devices
and the gates of the bottom devices, respectively.
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 32.
VDD
T-LINE
RFOUT
VGG2
RFIN
T-LINE
Figure 32. Architecture and Simplified Schematic
HMC8400
Though gate bias voltages are set internally via resistor connections
and/or a resistive voltage divider tap off of VDD, the VGG2 pad is
provided to allow the user a means of changing the gate bias of
the upper FETs. Application of a voltage to VGG2 changes the
voltage output by a resistive divider, thus altering the gate bias
of the upper FETs. Adjustment of the bias in this manner allows
the user a 30 dB gain control function. For gain control, VGG2
voltages within the range of −2 V through +2.6 V can be applied.
For VDD = 5.0 V dc, the VGG2 open-circuit voltage is
approximately 2.0 V.
Rev. A | Page 11 of 14

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