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Numéro de référence | CY14V116N | ||
Description | 16-Mbit (1024 K x 16) nvSRAM | ||
Fabricant | Cypress Semiconductor | ||
Logo | |||
1 Page
CY14V116N
16-Mbit (1024 K × 16) nvSRAM
Features
■ 16-Mbit nonvolatile static random access memory (nvSRAM)
❐ 30-ns and 45-ns access times
❐ Logically organized as 1024 K × 16
❐ Hands-off automatic STORE on power-down with only a
small capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
❐ RECALL to SRAM initiated by software or power-up
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ Sleep mode operation
■ Low power consumption
❐ Active current of 75 mA at 45 ns
❐ Standby mode current of 650 A
❐ Sleep mode current of 10 A
■ Operating voltage
❐ Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
■ Industrial temperature: –40 C to +85 C
■ 165-ball fine-pitch ball grid array (FBGA) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14V116N is a fast SRAM, with a nonvolatile
element in each memory cell. The memory is organized as
1024 K words of 16 bits each. The embedded nonvolatile
elements incorporate QuantumTrap technology, producing the
world’s most reliable nonvolatile memory. The SRAM can be
read and written an infinite number of times. The nonvolatile data
residing in the nonvolatile elements do not change when data is
written to the SRAM. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A0-A11
QUANTUMTRAP
4096 X 4096
STORE
STATIC RAM
ARRAY
4096 X 4096
RECALL
VCC VCAP VCCQ
POWER CONTROL
SLEEP MODE
CONTROL
ZZ
STORE / RECALL
CONTROL
HSB
SOFTWARE
DETECT
A2-A14
OE
CE
WE
[1]
DQ 0-DQ 15
COLUMN IO
COLUMN DECODER
BLE
BHE
ZZ
A12-A19
Note
1. In this datasheet, CE refers to the internal logical combination of CE1 and CE2, such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-75791 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015
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Pages | Pages 25 | ||
Télécharger | [ CY14V116N ] |
No | Description détaillée | Fabricant |
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