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PDF CY14V101Q3 Data sheet ( Hoja de datos )
| Número de pieza | CY14V101Q3 | |
| Descripción | 1 Mbit (128 K x 8) Serial SPI nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY14V101Q3
1 Mbit (128 K × 8) Serial SPI nvSRAM
Features
■ 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐ RECALL to SRAM initiated on power-up
(Power-Up RECALL) or by SPI instruction
(Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ High speed serial peripheral interface (SPI)
❐ 30 MHz clock rate
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4,1/2, or entire array
■ Low power consumption
❐ Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
❐ Average active current of 10 mA at 30 MHz operation
■ Industry standard configurations
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14V101Q3 combines a 1 Mbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cell provides highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down. On power-up, data is restored to the SRAM from
the nonvolatile memory (RECALL operation). Both STORE and
RECALL operations can also be initiated by the user through SPI
instruction.
For a complete list of related documentation, click here.
Logic Block Diagram
VCC VCCQ VCAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128 K X 8
SRAM ARRAY
128 K X 8
STORE
RECALL
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
Power Control
STORE/RECALL
Control
HSB
SO
Status register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67191 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 13, 2014
1 page  
CY14V101Q3
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power-down. This STORE makes use of an external capacitor
(VCAP) and enables the device to safely STORE the data in the
nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) instruction on page 13.
If AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status register. To resume normal functionality, the
WRSR instruction must be issued to update the nonvolatile bits
BP0, BP1 and WPEN in the Status Register.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. See DC Electrical Character-
istics on page 15 for the size of the VCAP.
Figure 2. AutoStore Mode
VCCQ VCC
0.1uF
VCCQ
VCC
0.1uF
CS VCAP
VSS
VCAP
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB Pin Operation
The HSB pin in CY14V101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware store
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.
Hardware RECALL (Power-up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Document #: 001-67191 Rev. *E
Page 5 of 24
5 Page 
CY14V101Q3
Write Protect (WP) Pin
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the status register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the status
register.
WP pin can be used along with WPEN and block protect bits
(BP1 and BP0) of the status register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to status register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the status register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the status register.
Table 6 summarizes all the protection features of this device
Table 6. Write Protection Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
X X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 LOW 1 Protected Writable Protected
1 HIGH 1 Protected Writable Writable
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the status register and the HSB pin.
Read Sequence (READ) instruction
The read operations on this device are performed by giving the
instruction on SI and reading the output on SO pin. The following
sequence needs to be followed for a read operation: After the CS
line is pulled LOW to select a device, the read opcode is
transmitted through the SI line followed by three bytes of
address. The Most Significant address byte contains A16 in bit 0
and other bits as ‘don’t cares’. Address bits A15 to A0 are sent
in the following two address bytes. After the last address bit is
transmitted on the SI pin, the data (D7-D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
CY14V101Q3 allows reads to be performed in bursts through
SPI which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x1FFFF) is reached, the address rolls over to
0x0000 and the device continues to read.
Write Sequence (WRITE) instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by 3 bytes of address and the data (D7-D0) which is to
be written. The Most Significant address byte contains A16 in bit
0 with other bits being ‘don’t cares’. Address bits A15 to A0 are
sent in the following two address bytes.
CY14V101Q3 enables writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address is incremented automatically.
The following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x1FFFF) is reached, the address rolls over to 0x0000
and the device continues to write. The WEN bit is reset to ‘0’ on
completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Figure 10. Read Instruction Timing
CS
SCK
0 1 2 34 5 67 0 1 23 45 6 7
20 21 22 23 0 1 2 3 4 5 6 7
Op-Code
17-bit Address
SI 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 A16 A3 A2 A1 A0
MSB
LSB
SO D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Document #: 001-67191 Rev. *E
Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CY14V101Q3.PDF ] | |
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