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PDF TW6874 Data sheet ( Hoja de datos )
| Número de pieza | TW6874 | |
| Descripción | Quad (SD/HD) SDI Receiver | |
| Fabricantes | Intersil | |
| Logotipo |  |
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DATASHEET
Quad (SD/HD) SDI Receiver with Adaptive Equalizer,
VC-2 Decoder and Audio CODEC
TW6874
The TW6874 is a quad (SD/HD) SDI receiver. It has four
independent channels, each consisting of an adaptive
equalizer, clock data recovery, audio decoder and VC-2
decompression engine. Each channel receives high speed
serial data over extended coaxial cable lengths and deserialize
the data into video/audio streams for the back-end device.
The video streams are output as: 8-bit BT.656 for SD; BT.1120
in 8/16 bit mode for HD. The audio streams are output
through an I2S audio digital interface in a multichannel
interleaving format. In addition to the extraction of embedded
SDI audio, the TW6874 incorporates a 5-channel audio ADC
decoder to decode analog audio inputs and output them
through the same I2S interface.
A visually lossless VC-2 (Dirac) compression/decompression
engine is implemented in the TW6872/TW6874 SDI Tx/Rx
pair to extend the reach of HD-SDI to that of SD-SDI. An
interrupt pin can be used to signal the host processor of
ancillary data packet detection. Finally, integrated audio test
patterns and PRBS checker ease system design and
implementation.
Applications
• SD/HD DVR
Features
• Quad (SD/HD) SDI receiver for standard (SD) and high (HD)
definition 10-bit component video
• Automatic SDI detection of SMPTE 259M Level C (SD-SDI),
SMPTE ST 292 (1.5G SDI) signals
• Each SDI input standard supported with ITU-R BT.656 (SD) or
ITU-R BT.1120 (1.5G) interface
• Converts 10-bit serial digital component video input to 8-bit
parallel video output
• Adaptive equalizer/clock data recovery/VC-2 decompression
engine for each channel
• 4 separate video output ports with BT.656/BT.1120 output
format
• 5-channel audio ADC (Analog-to-Digital Converter)
• Single multiplexed audio output DAC (Digital-to-Analog
Converter)
• Supports I2S master/slave interface for record output and
playback input with cascade
• I2C and SPI interface
• Pb-free (RoHS compliant) 256 ball LFBGA
TERMINATION NETWORK
1.0V 1.8V 3.3V
R AIN5
C
VO1 18
LR
SDI1P
VO2 18
75
C
R
SDI1N
VO3 18
VO4 18
BACK-END
CHIP (CODEC,
2.2µF
VIDEO MUX)
d
AIN1
I2S record 3
u
m
m
y
4.7k
I2S play 3
TW6874
d
u
m
m
TERMINATION
NETWORK
SDI2P
SDI2N
AIN2
IRQ
HOST
PROCESSOR
y
I2C/SPI
TERMINATION
NETWORK
SDIP3
SDIN3
AIN3
TERMINATION
NETWORK
SDIP4
SDIN4
AIN4
XTI
XTO
22pF
27MHz
22pF
AOUT
TESTEN
3.7k
8.2nF
0
FIGURE 1. TW6874 TYPICAL APPLICATION
March 25, 2015
FN8430.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
IAll other trademarks mentioned are the property of their respective owners.
1 page  
Pin Configuration
Analog Power
TW6874
TW6874
(256 BALL 13.5mmx13.5mm LFBGA)
TOP VIEW
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5
FN8430.1
March 25, 2015
5 Page 
Pin Descriptions (Continued)
PIN LOCATION
A2
PIN NAME
AVDD_CDR1
A1 AVSS_CDR1
H1 AVDD_CDR2
H2 AVSS_CDR2
J1 AVDD_CDR3
J2 AVSS_CDR3
T2 AVDD_CDR4
T1
C2, D4, E3, E4, F2, F3, F4, G3,
K3, K4, L2, L3, L4, M3, M4, P2
D1
AVSS_CDR4
AVSS_EQ
AVDD_REG1
D2 AVSS_REG1
E1 AVDD_REG2
E2 AVSS_REG2
M1 AVDD_REG3
M2 AVSS_REG3
N1 AVDD_REG4
N2 AVSS_REG4
H3 AVDD_BG
J3 AVSS_BG
C5 AVDD_TST1
C4 AVSS_TST1
P3 AVDD_TST4
N3 AVSS_TST4
P4 AVDD_DAC
N4 AVSS_DAC
T6 AVDD_AFE
R6 AVSS_AFE
T7 AVDD_FPLL10
R7 AVSS_FPLL10
P7 AVDD_FPLL18
TW6874
TYPE
DESCRIPTION
Analog Power 1.0V analog power supply for CDR. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for CDR. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for CDR. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for CDR. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for regulator. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for regulator. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for regulator. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for regulator. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for band-gap. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for test outputs. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for test outputs. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for audio DAC. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for audio AFE (Audio Front-End). Place a local 0.1µF
ceramic bypass capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.0V analog power supply for PLL. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Analog Ground Analog ground.
Analog Power 1.8V analog power supply for PLL. Place a local 0.1µF ceramic bypass
capacitor to the analog ground as close to the pin as possible.
Submit Document Feedback 11
FN8430.1
March 25, 2015
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TW6874.PDF ] | |
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