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PDF AD4003 Data sheet ( Hoja de datos )
| Número de pieza | AD4003 | |
| Descripción | 2 MSPS Precision SAR Differential ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
18-Bit, 2 MSPS
Precision SAR Differential ADC
AD4003
FEATURES
Throughput: 2 MSPS maximum
INL: ±1.0 LSB (±3.8 ppm) maximum
Guaranteed 18-bit no missing codes
Low power
9.5 mW at 2 MSPS (VDD only)
80 µW at 10 kSPS, 16 mW at 2 MSPS (total)
SNR: 100.5 dB typical at 1 kHz, 99 dB typical at 100 kHz
THD: −123 dB typical at 1 kHz, −100 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Differential analog input range: ±VREF
0 V to VREF with VREF between 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay
Guaranteed operation: −40°C to 125°C
Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: 3 mm × 3 mm LFCSP and 3 mm × 4.90 mm
MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4003 is a low noise, low power, high speed, 18-bit, 2 MSPS
precision successive approximation register (SAR) analog-to-
digital converter (ADC). It incorporates ease of use features that
lower the signal chain power, reduce signal chain complexity, and
enable higher channel density. The high-Z mode, coupled with a
long acquisition phase, eliminates the need for a dedicated high
power, high speed ADC driver, thus broadening the range of low
power precision amplifiers that can drive this ADC directly, while
still achieving optimum performance. The input span compression
feature enables the ADC driver amplifier and the ADC to operate
off common supply rails without the need for a negative supply
while preserving the full ADC code range. The low serial
peripheral interface (SPI) clock rate requirement reduces the
digital input/output power consumption, broadens processor
options, and simplifies the task of sending data across digital
isolation.
Operating from a 1.8 V supply, the AD4003 has a ±VREF fully differ-
ential input range with VREF ranging from 2.4 V to 5.1 V. The AD4003
consumes only 16 mW at 2 MSPS with a minimum of 75 MHz
SCK rate in turbo mode and achieves ±1.0 LSB (±3.8 ppm) INL
maximum, guaranteed no missing codes at 18 bits with 100.5 dB
typical SNR. The reference voltage is applied externally and can
be set independently of the supply voltage.
The SPI-compatible versatile serial interface features seven different
modes including the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus and provides an optional busy
indicator. The AD4003 is compatible with 1.8 V, 2.5 V, 3 V, and
5 V logic, using the separate VIO supply.
The AD4003 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +125°C. The device is
pin compatible with the 16-bit, 2 MSPS AD4000.
VREF
VREF/2
0
VREF
VREF/2
0
FUNCTIONAL BLOCK DIAGRAM
2.5V TO 5V
10µF
1.8V
REF
VDD
HIGH-Z
MODE
AD4003
IN+
18-BIT
SAR ADC
IN–
CLAMP
SPAN
COMPRESSION
TURBO
MODE
SERIAL
INTERFACE
STATUS
BITS
GND
VIO 1.8V TO 5V
SDI
SCK
SDO
CNV
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD4003
Parameter
fIN = 100 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
fIN = 400 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
REFERENCE
Voltage Range (VREF)
Current
OVERVOLTAGE CLAMP
IIN+/IIN−
VIN+/VIN− at Maximum IIN+/IIN−
VIN+/VIN− Clamp On/Off Threshold
Deactivation Time
REF Current at Maximum IIN+/IIN−
DIGITAL INPUTS
Logic Levels
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Current, IIL
Input High Current, IIH
Input Pin Capacitance
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Output Low Voltage, VOL
Output High Voltage, VOH
POWER SUPPLIES
VDD
VIO
Standby Current
Power Dissipation
VDD Only
REF Only
Test Conditions/Comments
Min
2 MSPS, VREF = 5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VIN+/VIN− > VREF
2.4
5.25
2.68
Data Sheet
Typ
99
−100
96.5
91.5
−94
90
10
1
1
1.1
5.4
3.1
5.4
2.8
360
100
Max
5.1
50
50
Unit
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
V
mA
mA
mA
V
V
V
V
ns
µA
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
−0.3
−0.3
0.7 × VIO
0.8 × VIO
−1
−1
6
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
pF
ISINK = 500 µA
ISOURCE = −500 µA
Serial 18 bits, twos complement
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
V
V
VDD = 1.8 V, VIO = 1.8 V, T = 25°C
VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
1 MSPS, high-Z mode enabled
2 MSPS, high-Z mode enabled
2 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
1.71
1.71
1.8 1.89
5.5
1.6
80
8
16 18.5
10
20 24.5
9.5
5.5
V
V
µA
µW
mW
mW
mW
mW
mW
mW
Rev. 0 | Page 4 of 33
5 Page 
AD4003
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.8 V; VIO = 3.3 V; VREF = 5 V; T = 25°C, high-Z mode disabled, span compression disabled and turbo mode enabled
(fS = 2 MSPS), unless otherwise noted.
1.0 0.4
0.8
0.6
+125°C
+25°C
–40°C
+125°C
0.3 +25°C
–40°C
0.2
0.4
0.2 0.1
00
–0.2 –0.1
–0.4
–0.2
–0.6
–0.8 –0.3
–1.0
0
32768 65536 98304 131072 163840 196608 229376 262144
CODE
Figure 5. INL vs. Code and Temperature, VREF = 5 V
–0.4
0
32768 65536 98304 131072 163840 196608 229376 262144
CODE
Figure 8. DNL vs. Code and Temperature, VREF = 5 V
1.0
0.8 +125°C
+25°C
0.6 –40°C
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32768 65536 98304 131072 163840 196608 229376 262144
CODE
Figure 6. INL vs. Code and Temperature, VREF = 2.5 V
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
+125°C
+25°C
–40°C
32768 65536 98304 131072 163840 196608 229376 262144
CODE
Figure 9. DNL vs. Code and Temperature, VREF = 2.5 V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0
HIGH-Z ENABLED
SPAN COMPRESSION ENABLED
32768 65536 98304 131072 163840 196608 229376 262144
CODE
Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
1.8
1.7 +125°C
+25°C
1.6 –40°C
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.5
3.0 3.5 4.0 4.5
REFERENCE VOLTAGE (V)
Figure 10. Transition Noise vs. Reference Voltage
5.0
Rev. 0 | Page 10 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD4003.PDF ] | |
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