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PDF MT18VDDT6472A Data sheet ( Hoja de datos )
| Número de pieza | MT18VDDT6472A | |
| Descripción | 512MB DDR SDRAM UNBUFFERED DIMM | |
| Fabricantes | Micron | |
| Logotipo |  |
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256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT18VDDT3272A – 256MB
MT18VDDT6472A – 512MB
MT18VDDT12872A – 1GB
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/modules
Features
• 184-pin dual in-line memory module (DIMM)
• Fast data transfer rates: PC3200
• CAS Latency 3
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB
(128 Meg x 72)
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (256MB), 7.8125µs (512MB, 1GB) maximum
average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
1.25in. (31.75mm)
OPTIONS
• Package
184-pin DIMM (Standard)
184-pin DIMM (Lead-free)
• Memory Clock/Speed, CAS Latency
5ns (200MHz), 400MT/s, CL = 3
• PCB
Standard 1.25in. (31.75mm)
MARKING
G
Y
-40B
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Table 5: Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40, 53,
55, 57, 60, 61, 64, 68, 69, 72,
73, 79, 80, 83, 84, 87, 88, 94,
95, 98, 99, 105, 106, 109,
110, 114, 117, 121, 123, 126,
127, 131, 133, 146, 147, 150,
151, 153, 155, 161, 162, 165,
166, 170, 171, 174, 175, 178,
179
92
181,182, 183
91
SYMBOL
DQ0–DQ63
SCL
SA0–SA2
SDA
1
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143, 156,
164, 172, 180
7, 38, 46, 70, 85, 108, 120,
148, 168
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152, 160,
176
184
9, 10, 71, 82, 90, 101, 102,
103, 113, 115 (256MB), 163,
167, 173
VREF
VDDQ
VDD
VSS
VDDSPD
NC
TYPE
Input/
Output
Data I/Os: Data bus.
DESCRIPTION
Input
Input
Input/
Output
Supply
Supply
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
SSTL_2 reference voltage.
DQ Power Supply: +2.6V ±0.1V.
Supply Power Supply: +2.6V ±0.1V.
Supply Ground.
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
— No Connect: These pins should be left unconnected.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
5 Page 
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
Table 8: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
CS# RAS# CAS# WE# ADDR
HXXX
X
L HHH
X
L L H H Bank/Row
L H L H Bank/Col
L H L L Bank/Col
L HH L
X
L L H L Code
L L LH
X
L L L L Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12
(256MB, 512MB) provide the op-code to be written to the selected mode register.
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
DM DQS
L Valid
HX
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet MT18VDDT6472A.PDF ] | |
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