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PDF MT4LSDT464LH Data sheet ( Hoja de datos )
| Número de pieza | MT4LSDT464LH | |
| Descripción | 32MB SMALL-OUTLINE SDRAM MODULE | |
| Fabricantes | Micron | |
| Logotipo |  |
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SMALL-OUTLINE
SDRAM MODULE
Features
• PC100 and PC133 compliant 144-pin, small-outline,
dual in-line memory module (SODIMM)
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 32MB (4Meg x 64), 64MB (8 Meg x 64), and 128MB
(16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 32MB and 64MB: 64ms, 4,096-cycle refresh
(15.625µs refresh interval); 128MB: 64ms, 8,192-
cycle refresh (7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1: Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE CLOCK
SETUP HOLD
MARKING FREQUENCY CL = 2 CL = 3 TIME TIME
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
6ns2
–
5.4ns
–
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
MT4LSDT464(L)H(I) – 32MB
MT4LSDT864(L)H(I) – 64MB
MT4LSDT1664(L)H(I) – 128MB
For the latest data sheet, please refer to the Micron® Web
site: www.micron.com/products/modules
Figure 1: 144-Pin SODIMM (MO-190)
Standard 1.00in. (25.40 mm)
Options
Marking
• Self Refresh Current
Standard
Low-Power
None
L1, 2
• Operating Temperature Range
Commercial (0°C to + 65°C)
Industrial (-40°C to +85°C)
None
I1, 2
• Package
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
G
Y1
• Memory Clock/CAS Latency
7.5ns (133 MHz)/CL = 2
-13E
7.5ns (133 MHz)/CL = 3
-133
10ns (100 MHz)/CL = 2
-10E
NOTE: 1. Contact Micron for product availability.
2. Low Power and Industrial Temperature options
not available concurrently; Industrial Tempera-
ture option available in -133 speed only.
Table 2: Address Table
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
32MB
4K
4 (BA0, BA1)
64Mb (4 Meg x16)
4K (A0–A11)
256 (A0–A7)
1 (S0#)
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0–A11)
512 (A0–A8)
1 (S0#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0–A12)
512 (A0–A8)
1 (S0#)
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
1 ©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information
PIN NUMBERS
3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,
16, 17, 18, 19, 20, 37, 38, 39,
40, 41, 43, 44, 47, 48, 49, 50,
51, 52, 53, 54, 83, 84, 85, 86,
87, 88, 89, 90, 93, 94, 95, 96,
97, 98, 99, 100, 121, 122, 123,
124, 125, 126, 127, 128, 131,
132, 133, 134, 135, 136, 137,
138
11, 12, 27, 28, 45, 46, 63, 64,
81, 82, 101, 102, 113, 114, 129,
130, 143, 144
1, 2, 21, 22, 35, 36, 55, 56, 75,
76, 91, 92, 107, 108, 119, 120,
139, 140
70 (32MB, 64MB), 72, 73
57, 58, 59, 60, 68, 71, 74, 77,
78, 79, 80
SYMBOL
DQ0–DQ63
VDD
VSS
NC
DNU
TYPE
Input/ Data I/O: Data bus.
Output
DESCRIPTION
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
– Not Connected: These pins should be left unconnected.
– Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
5 Page 
Commands
The Truth Table provides a quick reference of avail-
able commands. This is followed by written descrip-
tion of each command. For a more detailed des-
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
cription of commands and operations, refer to the
64Mb, 128Mb, or 256Mb SDRAM component data
sheet.
Table 8: Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION)
CS# RAS# CAS# WE# DQMB ADDR
DQ NOTES
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
H
L
L
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
L
L
L
L
X
H
L
H
H
H
L
XX
X
X
X
HH
X
X
X
HH
X
Bank/
Row
X
L H L/H8 Bank/Col X
L L L/H8 Bank/Col Valid
HL
HL
X
X
X
Code
Active
X
1
2
2
3
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
LL
LL
LH
LL
XX X
X Op-code
X
4, 5
6
Write Enable/Output Enable
––
––
L
–
Active
7
Write Inhibit/Output High-Z
––
––
H
–
High-Z
7
NOTE:
1. A0–A11 (32MB and 64MB) , or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank
is made active.
2. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH enables the auto precharge fea-
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for 32MB and 64MB, A12 should be driven low.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MT4LSDT464LH.PDF ] | |
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