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PDF MBM29F016A-12 Data sheet ( Hoja de datos )
| Número de pieza | MBM29F016A-12 | |
| Descripción | 16M (2M x 8) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
16M (2M × 8) BIT
DS05-20844-4E
MBM29F016A-70/-90/-12
s FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
• 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Uniform sectors of 64 K bytes each
Any combination of sectors can be erased. Also supports full chip erase.
• Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
• Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 4 adjacent sectors of 64 K bytes each)
• Temporary sector groups unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
1 page  
s PRODUCT LINE UP
Part No.
Ordering Part No.
VCC = 5.0 V ±5%
VCC = 5.0 V ±10%
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s BLOCK DIAGRAM
MBM29F016A-70/-90/-12
MBM29F016A
-70 —
— -90
70 90
70 90
40 40
—
-12
120
120
50
VCC
VSS
WE
RESET
CE
OE
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
DQ0 to DQ7
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
A0 to A20
STB Y-Decoder
Low VCC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F016A-70/-90/-12
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
Table 5 Sector Group Addresses
A20 A19 A18
000
001
010
011
100
101
110
111
Sectors
SA0 to SA3
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SA28 to SA31
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29F016A features hardware sector group protection. This feature will disable both program and erase
operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see
Table 5). The sector group protection feature is enabled using programming equipment at the user's site. The
device is shipped with all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL. The sector addresses (A20, A19, and A18) should be set to the sector to be protected.
Tables 4 and 5 define the sector address for each of the thirty two (32) individual sectors, and the sector group
address for each of the eight (8) individual group sectors. Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held
constant during the WE pulse. See figures 14 and 21 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A20, A19, and A18) while (A6, A1, A0) = (0,
1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce
00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES.
Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A20, A19, and
A18) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See
Table 3 for Autoselect codes.
11
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| PDF Descargar | [ Datasheet MBM29F016A-12.PDF ] | |
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