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PDF MBM29F040A-12 Data sheet ( Hoja de datos )
| Número de pieza | MBM29F040A-12 | |
| Descripción | FLASH MEMORY 4M 512K x 8 BIT | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
4M (512K × 8) BIT
MBM29F040A - 70/-90/-12
DS05–20810–3E
s DISTINCTIVE CHARACTERISTICS
• Single 5.0 V read, write and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
Note: If there are special requirements not specified above (such as DIP package), please contact Fujitsu
sales office.
• Minimum 100,000 write/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low power consumption
20 mA typical active read current
30 mA typical write/erase current
25 µA typical standby current
• Low Vcc write inhibit ≤ 3.2 V
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
Embedded Erase™ and Embedded Program™ are trademarks of Advanced Micro Devices, Inc.
1 page  
MBM29F040A -70/-90/-12
s PRODUCT SELECTOR GUIDE
Part No.
Ordering Part No. VCC = 5.0 V ± 5 % MBM29F040A – 70
VCC = 5.0 V ± 10 %
—
Max. Access Time (ns)
70
CE Access (ns)
70
OE Access (ns)
30
MBM29F040A
—
MBM29F040A – 90
90
90
35
—
MBM29F040A – 12
120
120
50
s BLOCK DIAGRAM
V CC
V SS
WE
CE
OE
DQ 0 to DQ 7
Erase Voltage
Generator
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
STB
Data Latch
Logic
A0 to A18
V CC Detector
Timer
STB Y-Decoder
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F040A -70/-90/-12
DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A16, A17, and
A18) are the sector address will produce a logical “1” at DQ0 for a protected sector. See Table 3 for Autoselect
codes.
Table 5 MBM29F040A Command Definitions
Command
Sequence
Read/Reset
Bus First Bus Second Bus Third Bus
Write Write Cycle Write Cycle Write Cycle
Cycles
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset*
Read/Reset*
Autoselect
1 XXXXH F0H — — — — — — — — — —
3 5555H AAH 2AAAH 55H 5555H F0H RA RD — — — —
3 5555H AAH 2AAAH 55H 5555H 90H — — — — — —
Byte Program
Chip Erase
4 5555H AAH 2AAAH 55H 5555H A0H PA PD — — — —
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
Sector Erase Suspend
Erase can be suspended during sector erase with Addr (H or L). Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr (H or L). Data (30H)
Notes: 1. Address bits A0 to A15 = X = H or L for all address commands except for Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the
WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, and A16 will uniquely select any
sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE .
*: Either of the two reset commands will reset the device.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to
read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0) and
Erase Resume (30) commands are valid only while the Sector Erase operation is in progress.
11
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| PDF Descargar | [ Datasheet MBM29F040A-12.PDF ] | |
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