PDF MBM29LV008BA-12 Data sheet ( Hoja de datos )

Número de pieza	MBM29LV008BA-12
Descripción	8M (1M x 8) BIT FLASH MEMORY
Fabricantes	Fujitsu
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No Preview Available ! FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 8M (1M × 8) BIT DS05-20858-4E MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12 s FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection Set function by Extended sector protection command • Temporary sector unprotection Temporary sector unprotection via the RESET pin Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 1 page MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12 s PRODUCT LINE UP Part No. Ordering Part No. VCC = 3.3 V +0.3 V –0.3 V VCC = 3.0 V +0.6 V –0.3 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) s BLOCK DIAGRAM MBM29LV008TA/MBM29LV008BA -70 — — — -90 -12 70 90 120 70 90 120 30 35 50 VCC VSS WE RESET CE OE RY/BY Buffer RY/BY Erase Voltage Generator DQ 0 to DQ 7 Input/Output Buffers State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic STB Data Latch A0 to A19 STB Y-Decoder Low VCC Detector Timer for Program/Erase Address Latch X-Decoder Y-Gating Cell Matrix 5 5 Page MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Table 4 Sector Address Tables (MBM29LV008TA) A18 A17 A16 A15 A14 A13 0 0 0XXX 0 0 1XXX 0 1 0XXX 0 1 1XXX 1 0 0XXX 1 0 1XXX 1 1 0XXX 1 1 1XXX 0 0 0XXX 0 0 1XXX 0 1 0XXX 0 1 1XXX 1 0 0XXX 1 0 1XXX 1 1 0XXX 1 1 1 0XX 111100 111101 11111X Address Range 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to F7FFFH F8000H to F9FFFH FA000H to FBFFFH FC000H to FFFFFH 11 11 Page

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