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PDF AT84AD004 Data sheet ( Hoja de datos )
| Número de pieza | AT84AD004 | |
| Descripción | DUAL 8-BIT 500 MSPS ADC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Dual ADC with 8-bit Resolution
• 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode
• Single or 1:2 Demultiplexed Output
• LVDS Output Format (100Ω)
• 500 mVpp Analog Input (Differential Only)
• Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
• Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
• LQFP144 Package
• Temperature Range:
– 0°C < TA < 70°C (Commercial Grade)
– -40°C < TA < 85°C (Industrial Grade)
• 3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Performance
• Low Power Consumption: 0.7W per Channel
• Power Consumption in Standby Mode: 120 mW
• 1 GHz Full Power Input Bandwidth (-3 dB)
• SNR = 43 dB Typ (7.0 ENOB), THD = -53 dBc, SFDR = -55 dBc at Fs = 500 Msps
Fin = 250 MHz
• 2-tone IMD3: -54 dBc (249 MHz, 251 MHz) at 500 Msps
• DNL = 0.25 LSB, INL = 0.5 LSB
• Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
• Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
• Low Bit Error Rate (10-15) at 500 Msps
Application
• Instrumentation
• Satellite Receivers
• Direct RF Down Conversion
• WLAN
Dual 8-bit
500 Msps ADC
AT84AD004
Smart ADC
5390A–BDC–06/04
1
1 page  
Figure 3. Dual Channel Digital Oscilloscope Application
Channel B
A
Channel A
A
Channel Mode
Selection
DAC
Gain
DAC
Offset
ADC B
DAC
Offset
DAC
Gain
ADC A
DACs
Smart Dual
ADC
DACs
AT84AD004
FISO
RAM
µP
Display
Clock
Selection
Timing
Circuit
Absolute Maximum Ratings
Parameter
Analog positive supply voltage
Digital positive supply voltage
Output supply voltage
Maximum difference between VCCA and VCCD
Minimum VCCO
Analog input voltage
Digital input voltage
Clock input voltage
Maximum difference between VCLK and VCLKB
Maximum junction temperature
Storage temperature
Lead temperature (soldering 10s)
Symbol
VCCA
VCCD
VCCO
VCCA to VCCD
VCCO
VINI or VINIB
VINQ or VINQB
VD
VCLK or VCLKB
VCLK - VCLKB
TJ
Tstg
Tleads
Value
3.6
3.6
3.6
± 0.8
1.6
1/-1
-0.3 to VCCD + 0.3
-0.3 to VCCD + 0.3
-2 to 2
125
-65 to 150
300
Unit
V
V
V
V
V
V
V
V
V
°C
°C
°C
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
5390A–BDC–06/04
5
5 Page 
AT84AD004
Table 5. Switching Performances
Parameter
Symbol
Min
Typ
Max
Switching Performance and Characteristics - See “Timing Diagrams” on page 12.
Maximum operating clock frequency
FS 500
Minimum clock frequency (no transparent mode)
Minimum clock frequency (with transparent mode)
FS
10
1
Minimum clock pulse width [high]
(No transparent mode)
TC1 0.4 1 50
Minimum clock pulse width [low]
(No transparent mode)
TC2 0.4 1 50
Aperture delay: nominal mode with ISA & FiSDA
TA
1
Aperture uncertainty
Jitter
0.4
Data output delay between input clock and data
TDO
3.8
Data Ready Output Delay
TDR
3
Data Ready Reset to Data Ready
TRDR
2
Data Output Delay with Data Ready
TD2
1/2 Fs
+Tdrda
Data Ready (CLKO) Delay Adjust (140 ps steps)
Tdrda range
-560 to 420
Output skew
50 100
Output rise/fall time for DATA (20% - 80%)
TR/TF
300
350
500
Output rise/fall time for DATA READY (20% - 80%)
TR/TF
300
350
500
Data pipeline delay (nominal mode)
Data pipeline delay (nominal mode) in S/H
transparent mode
TPD
3 (port B)
3.5 (port A, 1:1 DMUX mode)
4 (port A, 1:2 DMUX mode)
2.5 (port B)
3 (port A, 1:1 DMUX mode)
3.5 (port A, 1:2 DMUX mode)
DDRB recommended pulse width
1
Unit
Msps
Msps
Ksps
ns
ns
ns
ps (rms)
ns
ns
ns
ps
ps
ps
ps
ps
Clock cycles
ns
5390A–BDC–06/04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT84AD004.PDF ] | |
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