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| Número de pieza | NUC945ADN | |
| Descripción | Microcontroller | |
| Fabricantes | nuvoton | |
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NUC945ADN
32-BIT ARM926EJ-S BASED MCU
NUC945ADN
32-bit ARM926EJ-S Based Microcontroller
Product Data Sheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ARM926-based system design. Nuvoton
assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice..
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: Jun. 18, 2010
1 Revision: A5
1 page  
NUC945ADN
32-BIT ARM926EJ-S BASED MCU
2 Features
Architecture
Efficient and powerful ARM926EJ-S core with fully 16/32-bit RISC architecture
Little Endian mode supported
8K-byte I-cache and 8K-byte D-cache with MMU
Power management
Programmable clock enable for individual peripherals
IDLE mode to halt ARM Core and keep peripheral working
Power-Down mode to stop all clocks included external crystal oscillator.
Exit IDLE/Power-Down by interrupts
PLL
Supports one on-chip PLLs
The external clock can be multiplied by on-chip PLL to provide high frequency system clock
The input frequency range is 4-30MHz; 15MHz is preferred.
Programmable clock frequency
Wakeup by interrupt, USB device.
Advanced Interrupt Controller
31 interrupt sources, including 2 external interrupt sources
Programmable normal or fast interrupt mode (IRQ, FIQ)
Programmable as either edge-triggered or level-sensitive for 2 external interrupt sources
Programmable as either low-active or high-active for 2 external interrupt sources
Priority methodology is encoded to allow for interrupt daisy-chaining
Automatically mask out the lower priority interrupt during interrupt nesting
Automatically clear the interrupt flag when the interrupt source is programmed to be edge-triggered
External Bus Interface
8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/O
Programmable access cycle (0-7 wait cycle)
Four-word depth write buffer
Ethernet MAC Controller
100/10-Mbps operation
DMA engine with burst mode
MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
Full compliance with IEEE standard 802.3
RMII interface only
Station Management Signaling
On-Chip CAM (up to 16 destination addresses)
Full-duplex mode with PAUSE feature
Long/short packet modes
5
Publication Release Date: Jun. 18, 2010
Revision: A5
5 Page 
NUC945ADN
Pin Name
VSS
32-BIT ARM926EJ-S BASED MCU
IO Type Num. Description
G 3,9, IO Buffer and Core ground (0V)
12,
42,
61,
64,
70,
74,
81,
101,11
3,120
4.2 GPIO Share Pin Description
In this chip, there are GPIOD~GPIOH groups for general IO control. All of GPIO pins are shared with the
other interface and define as the following
GPIOD (7 pins)
GPIOD[0]
GPIOD[1]
GPIOD[2]
GPIOD[3]
GPIOD[4]
GPIOD[5]
GPIOD[6]
GPIOE (2 pins)
GPIOE[0]
GPIOE[1]
GPIOF (10 pins)
GPIOF [0]
GPIOF [1]
GPIOF [3:2]
GPIOF [4]
GPIOF [5]
GPIOF [7:6]
GPIOF [8]
GPIOF [9]
GPIOH (2 pins)
GPIOH[1:0]
SD(SDIO) /
Memory Stick Interface
SD_CMD /
MS_BS
SD_CLK /
MS_CLK
SD_DAT0 /
MS_DAT0
SD_DAT1 /
MS_DAT1
SD_DAT2 /
MS_DAT2
SD_DAT3 /
MS_DAT3
SD_CDn /
MS_CDn
UART Interface
TXD0
RXD0
RMII Interface
PHY_MDC
PHY_MDIO
PHY_TXD [1:0]
PHY_TXEN
PHY_REFCLK
PHY_RXD [1:0]
PHY_CRSDV
PHY_RXERR
nIRQ Interface
nIRQ[1:0]
11
Publication Release Date: Jun. 18, 2010
Revision: A5
11 Page | ||
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| PDF Descargar | [ Datasheet NUC945ADN.PDF ] | |
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