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PDF NUC960ADN Data sheet ( Hoja de datos )
| Número de pieza | NUC960ADN | |
| Descripción | Microcontroller | |
| Fabricantes | nuvoton | |
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NUC960ADN
32-BIT ARM926EJ-S BASED MCU
NUC960ADN
32-bit ARM926EJ-S Based Microcontroller
Product Data Sheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NUC960ADN-based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice..
For additional information or questions, please contact: Nuvoton Technology Corporation.
1 Publication Release Date: Jun. 18, 2010
Revision: A3
1 page  
NUC960ADN
32-BIT ARM926EJ-S BASED MCU
1. GENERAL DESCRIPTION
This chip is built around an outstanding CPU core: the 16/32 ARM926EJ-S RISC processor designed by
Advanced RISC Machines, Ltd. The ARM926EJ-S core, offers 8K-byte I-cache and 8K-byte D-cache with
MMU. One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost and one PCI Interface
is used to extend the PCI peripheral device. It is suitable for a high end, high performance and low cost
related products as well as general purpose applications.
The following integrated on-chip functions are described in detail in this document.
Main Function
CPU
ARM926EJ-S
Platform
Programmable PLL System Clock Synthesizer
AMBA Peripherals
Timer, Watchdog Timer
Advanced Interrupt Controller
General DMA Controller
External Bus Interface Controller
Networking
Ethernet MAC Controller
USB Interface
USB 1.1/2.0 High/Full/Low Speed Host
Controller
USB 2.0 High/Full Speed Device Controller
Peripheral & Misc. GPIO
UART/HS-UART
USI (SPI/uWire)
I2C (Master) Controller
PCI Host Controller
5 Publication Release Date: Jun. 18, 2010
Revision: A3
5 Page 
NUC960ADN
32-BIT ARM926EJ-S BASED MCU
4. PIN ASSIGNMENT
Table 4.1 NUC960ADN Pins Assignment
Pad Name
NUC960ADN
Clock & Reset
( 5 pins )
EXTAL15M
XTAL15M
EXTAL48M0
XTAL48M0
nRESET
102
103
209
208
1
TAP Interface
( 5 pins )
TMS
TDI
TDO
TCK
nTRST
10
11
12
13
14
External Bus Interface
( 71 pins )
MA [21:0]
MD [31:0]
nWBE [3:0] /
SDQM [3:0]
nSCS [1:0]
nSRAS
nSCAS
MCKE
nSWE
MCLK
nWAIT
nBTCS
nECS [2:0]
nOE
60-48,46-38
100–98,95–88,86,84–78,75–63
32-29
23-22
35
36
33
34
25
16
21
20-18
17
Ethernet RMII Interface
PHY_MDC /
GPIOF[0]
PHY_MDIO /
GPIOF[1]
177
178
( 10 pins )
11 Publication Release Date: Jun. 18, 2010
Revision: A3
11 Page | ||
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