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PDF N551C321 Data sheet ( Hoja de datos )
| Número de pieza | N551C321 | |
| Descripción | 32-Mbit Mask ROM | |
| Fabricantes | nuvoton | |
| Logotipo |  |
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N551C321
Table of Contents-
1. GENERAL DESCRIPTION.......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. BLOCK DIAGRAM ...................................................................................................................... 3
4. PIN DESCRIPTION..................................................................................................................... 3
5. ABSOLUTE MAXIMUM RATINGS.............................................................................................. 4
6. ELECTRICAL CHARACTERISTICS ........................................................................................... 4
7. APPLICATION CIRCUIT ............................................................................................................. 6
7.1 W551C Mode..................................................................................................................... 6
7.2 SPI Mode ........................................................................................................................... 7
8. REVISION HISTORY .................................................................................................................. 7
-1-
1 page  
N551C321
Select lead time
Data input setup time
Data input hold time
Data output valid time
Tssb
Tsui
Thdi
Tvdo
100 nS
20 nS
20 nS
85 nS
SPI Mode Interface
CSB
SCK
Tssb
SDI
Tsui
SDO
Thdi
(Hi impedance)
Tsck
Tvdo
Tsse
Tdbo
Thdo
Tssh
W551C Mode Interface
(VDDVSS = 4.5V, TA = 25 C; unless otherwise specified)
PARAMETER
Clock frequency of ADDR
Clock frequency of CLK
SYM.
FADDR
FCLK
CONDITIONS
VDD = 3.0V
VDD < 3.0V
MIN.
-
-
VDD ≧ 3.0V
Interval time between
ADDR and CLK
Interval between DATA to
another pin active
Data access time
Data setup time
Data hold time
Transmission time
between DATA1 and
DATA2
PS switch time
CS switch time
TI
TCFA
TRA
TAS
TRH
TAH
TD12
TD21
TPS1
TPS2
TcS1
TcS2
Read mode
-
Read mode
Address shift-in
Read mode
Address shift-in
Cascade Mode,
VDD=2.4V
Read mode
Read mode
1
10
-
40
0
10
35
20
500
500
500
500
TYP.
-
-
-
-
-
-
-
-
-
MAX.
6
1
1.5
-
-
500
-
-
-
-
--
--
UNIT
MHz
MHz
uS
uS
nS
nS
nS
nS
nS
nS
nS
-5-
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet N551C321.PDF ] | |
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