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PDF BT848 Data sheet ( Hoja de datos )
| Número de pieza | BT848 | |
| Descripción | Single-Chip Video Capture for PCI | |
| Fabricantes | ETC | |
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Advance Information
This document contains information on a product under development.
The parametric information contains target parameters that are subject to change.
Bt848/848A/849A
Single-Chip Video Capture for PCI
Bt848 is a complete, low cost single-chip solution for analog
NTSC/PAL/SECAM video capture on the PCI bus. As a bus master, Bt848 does
not require any local memory buffers to store video pixel data which signifi-
cantly minimizes the hardware cost for this architecture. Bt848 takes advantage
of the PCI-based system’s high bandwidth and inherent multimedia capability. It
is designed to be interoperable with any other PCI multimedia device at the
component or board level, thus enabling video capture and overlay capability to
be added to PCI systems in a modular fashion at low cost. The Bt848 solution is
independent of the PCI system bus topology and may be used in a variety of sys-
tem bus organizations: directly on a motherboard planar bus, on a card for a pla-
nar or secondary bus.
The Bt848A/849A are fully backward compatible enhancements to the
Bt848. The Bt848A and 849A both include all the functionality of the Bt848,
while adding support for peaking, single crystal operation, and digital camera
support.
Functional Block Diagram
XTAL
MUXIN
MUXOUT
SYNCDET
REFOUT
Analog
Mux
AGC
YIN 40 MHz
ADC
40 MHz
CIN ADC
Ultralock™
and
Clock Generation
Video Timing
Unit
IIC
Horizontal, Vertical
and Temporal
Scaling
Pixel Format
Conversion
JTAG
PCI I/F
Target
Luma-Chroma
Separation
and
Chroma Demod
630 Byte FIFO
DMA Controller
Digital Camera
Input (Bt848A/849A)
and GPIO Port
Initiator
Distinguishing Features
• Fully PCI Rev. 2.1 compliant
• Auxiliary GPIO data port and video data
port
• Supports image resolutions up to
768x576 (full PAL resolution)
• Supports complex clipping of video
source
• Zero wait state PCI burst writes
• Field/frame masking support to throttle
bandwidth to target
• Multiple YCrCb and RGB pixel
formats supported on output
• Supports NTSC/SECAM/PAL analog
input
• Image size scalable down to icon using
vertical & horizontal interpolation
filtering
• Multiple composite and S-video inputs
• Supports different destinations for even
and odd fields
• Supports different color space/scaling
factors for even and odd fields
• Support for mapping of video to 225
color palette
• VBI data capture for closed captioning,
teletext and intercast data decoding
Additional Features
in Bt848A/849A Only
• Supports peaking
• Requires only one crystal
• Digital camera support through GPIO
port
• Support for WST decode (Bt849A only)
Applications
• PC TV
• Intercast receiver
• Desktop video phone
• Motion video capture
• Still frame capture
• Teletext/Intertext
• VBI data services capture
Brooktree® Brooktree Division • Rockwell Semiconductor Systems, Inc. • 9868 Scranton Road • San Diego, CA 92121-3707
619-452-7580 • 1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: [email protected] • L848A_A
1 page  
Bt848/848A/849A
Single-Chip Video Capture for PCI
TABLE OF CONTENTS
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
General Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
GPIO SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Digital Video in Support (Bt848A/849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Latch-up Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Vendor and Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Command and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Revision ID and Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Base Address 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register . . . . . . . . . . . . . . . . . . . . . . 89
Local Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Input Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Temporal Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MSB Cropping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Vertical Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Vertical Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Horizontal Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Horizontal Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Horizontal Scaling Register, Upper Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Brooktree®
L848A_A
v
5 Page 
FUNCTIONAL
DESCRIPTION
Functional Overview
Video Capture
Over PCI Bus
The Bt848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video
decoder, scaler, DMA controller, and PCI Bus master on a single device.
Bt848/848A/849A can place video data directly into host memory for video cap-
ture applications and into a target video display frame buffer for video overlay ap-
plications. As a PCI initiator, Bt848/848A/849A can take control of the PCI bus as
soon as it is available, thereby avoiding the need for on-board frame buffers.
Bt848/848A/849A contains a pixel data FIFO to decouple the high speed PCI bus
from the continuous video data stream. Figure 1 shows a block diagram of the
Bt848/848A/849A, and Figure 2 shows a detailed block diagram of the decoder
and scaler sections.
The video data input may be scaled, color translated, and burst transferred to a
target location on a field basis. This allows for simultaneous preview of one field
and capture of the other field. Alternatively, Bt848/848A/849A is able to capture
both fields simultaneously or preview both fields simultaneously. The fields may
be interlaced into memory or sent to separate field buffers.
The Bt849A includes all the capability in the Bt848A and adds support for WST
decoding (the encoding method for European based Teletext). The Bt849A imple-
ments a significant amount of WST decoding in S/W ensuring a very low cost TV
card for use in locations requiring Teletext
See Table 1 for a comparison of the Bt848/848A/849A.
Supports
Intel Intercast™
The Bt848/848A/849A fully supports the Intel Intercast technology.
Intel Intercast technology combines the rich programming of television and the
exciting world of the Internet on your PC. Imagine watching a news broadcast and
simultaneously getting a Web page providing a historical perspective. Or viewing
a music video and ordering tickets on the Internet for the band’s next appearance
in your area. Or enjoying a favorite show and getting special web pages associated
with that program. Now your PC can let you interact with television in all kinds of
new and exciting ways.
Brooktree®
L848A_A
1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BT848.PDF ] | |
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