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Número de pieza | AT6010ALV-4QC | |
Descripción | Coprocessor Field Programmable Gate Arrays | |
Fabricantes | ATMEL Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AT6010ALV-4QC (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
No Preview Available ! AT6000/LV Series
Features
• High Performance
System Speeds > 100 MHz
Flip-Flop Toggle Rates > 250 MHz
1.2 ns/1.5 ns Input Delay
3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
• Thousands of Registers
•• Cache Logic® Design
Complete/Partial In-System Reconfiguration
No Loss of Data or Machine State
Adaptive Hardware
• Low Voltage and Standard Voltage Operation
5.0 (VCC = 4.75V to 5.25V)
• 3.3 (VCC = 3.0V to 3.6V)
Automatic Component Generators
Reusable Custom Hard Macro Functions
• Very Low Power Consumption
Standby Current of 500 µA/ 200 µA
Typical Operating Current of 15 to 170 mA
• Programmable Clock Options
Independently Controlled Column Clocks
Independently Controlled Column Resets
Clock Skew Less Than 1 ns Across Chip
• Independently Configurable I/O (PCI Compatible)
TTL/CMOS Input Thresholds
Open Collector/Tri-state Outputs
Programmable Slew-Rate Control
I/O Drive of 16 mA (combinable to 64 mA)
• Easy Migration to Atmel Gate Arrays for High Volume Production
Description
AT6000 Series SRAM-Based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic®, which provides the
user with the ability to implement adaptive hardware and perform hardware accelera-
tion.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O. (continued)
AT6000 Series Field Programmable Gate Arrays
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002
6,000
1,024
1,024
96
15-30
32 x 32
AT6003
9,000
1,600
1,600
120
25-45
40 x 40
AT6005
15,000
3,136
3,136
108
40-80
56 x 56
AT6010
30,000
6,400
6,400
204
85-170
80 x 80
Coprocessor
Field
Programmable
Gate Arrays
AT6000 and AT6000LV Se-
ries
0264E
2-3
1 page Figure 5a. Combinatorial Physical States
Li Li A
Li
B
A, Lo B A, Lo B A, Lo B A, Lo B
A Li B A Li B A Li
A Li
A, Lo B
A Li
A, Lo B
A, Lo B
A, Lo B
A, Lo B
Li B
Li B Li B
A Li
A, Lo B
A Li B
A, Lo B
A, Lo
A, Lo
A, Lo B
A, Lo B
A Li B A
B Li
B A Li B
A Li B
A, Lo B A, Lo B
A, Lo B
Figure 5b. Register States
AA
A, Lo B
Li
D
Q "0"
A, Lo B
D
Q
D
Q
A Li
A, Lo B
Li B
A, Lo B
A Li
10
A, Lo
B
D
Q
A, Lo B
D
Q
A, Lo B
AB
D
Q
A, Lo
D
Q
A, Lo
Li B
A Li B
D
Q
A, Lo B
D
Q
A, Lo B
D
Q
A, Lo B
A Li B
10
D
Q
A, Lo
AT6000/LV Series
Figure 5c. Physical Constants
"0" "0"
"0" "1"
"1" "0"
"1" "1"
A, Lo B
A, Lo B
A, Lo B
A, Lo B
Figure 6a. Two-Input AND Feeding XOR
A Li B
A
Figure 6b. Cell Configuration (A•L) XOR B
2-7
5 Page AT6000/LV Series
Pinout Assignment (Continued)
Left Side (Top to Bottom) (Continued)
AT6002
AT6003
AT6005
AT6010
84 100 132 144
PLCC VQFP PQFP TQFP
—
—
—
I/O9(A)
————
—
—
—
I/O8(B)
————
I/O3(A) or D1
I/O2(B)
I/O4(A) or D1
I/O3(A)
I/O3(A) or D1
I/O2(A)
I/O7(A) or D1
I/O6(A)
30 23 47 32
— — 48 33
—
—
—
I/O5(A)
————
—
—
—
I/O4(B)
————
—
I/O1(A) or D0
I/O2(B)
I/O1(A) or D0
—
I/O1(A) or D0
I/O3(A)
I/O2(A) or D0
— — — 34
31 24 49 35
—
CCLK
—
CCLK
—
CCLK
I/O1(A)
CCLK
————
32 25 50 36
Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.
2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.
180
CPGA
P2
—
J1
K1
L1
—
M1
N1
P1
R1
208 240
PQFP PQFP
45 51
— 52
46 53
47 54
48 55
— 56
49 57
50 58
51 59
52 60
AT6002
CON
—
I/O96(A)
—
—
—
—
—
—
I/O95(A) or CSOUT
—
—
I/O94(B)
I/O93(A)
—
—
I/O92(B)
I/O91(A) or CHECK
—
I/O90(B)
I/O89(A) or ERR
I/O88(B)
—
I/O87(A)
GND
I/O86(A)
—
—
I/O85(A)
CS
I/O84(B)
AT6003
CON
—
I/O120(A)
I/O119(B)
—
—
—
—
I/O118(A)
I/O117(A) or CSOUT
—
—
I/O116(A)
I/O115(A)
—
—
I/O114(B)
I/O113(A) or CHECK
—
I/O112(B)
I/O111(A) or ERR
I/O110(B)
—
I/O109(A)
I/O108(B)
GND
I/O107(A)
—
I/O106(B)
I/O105(A)
CS
I/O104(A)
Bottom Side (Left to Right)
AT6005
AT6010
84 100
PLCC VQFP
CON
CON
33 26
—
I/O204(A)
——
I/O108(A)
I/O203(A)
34 27
—
I/O202(A)
——
—
I/O201(B)
——
—
VCC
——
—
I/O200(A)
——
—
GND
——
I/O107(A)
I/O199(A)
——
I/O106(A) or CSOUT I/O198(A) or CSOUT 35
28
—
I/O197(B)
——
—
I/O196(A)
——
I/O105(A)
I/O195(A)
——
I/O104(A)
I/O194(A)
36 29
—
I/O193(B)
——
—
I/O192(A)
——
I/O103(A)
I/O191(A)
— 30
I/O102(A) or CHECK I/O190(A) or CHECK 37
31
—
I/O189(B)
——
I/O101(A)
I/O188(A)
——
I/O100(A) or ERR
I/O187(A) or ERR
38
32
I/O99(A)
I/O186(A)
— 33
—
I/O185(B)
——
I/O98(A)
I/O184(A)
39 34
I/O97(A)
I/O183(A)
GND
GND
40 35
I/O96(A)
I/O182(A)
41 36
—
I/O181(B)
——
—
I/O180(A)
——
I/O95(A)
I/O179(A)
42 37
CS CS 43 38
I/O94(A)
I/O178(A)
44 39
132
PQFP
51
—
52
—
—
—
—
—
53
54
—
—
55
56
—
—
57
58
—
59
60
61
—
62
63
64
65
—
—
66
67
68
144
TQFP
37
—
38
39
—
—
—
—
40
41
—
—
42
43
—
—
44
45
—
46
47
48
—
49
50
51
52
—
53
54
55
56
180
CPGA
M5
M6
M7
R2
—
PWR (1)
R3
GND (2)
R5
R6
—
R7
P3
P4
—
P5
P6
P7
—
N4
N5
N6
—
N7
M8
GND (2)
M9
—
M10
M11
L8
M12
208 240
PQFP PQFP
53 61
54 62
55 63
56 64
— 65
57 66
58 67
59 68
60 69
61 70
— 71
62 72
63 73
64 74
— 75
65 76
66 77
67 78
— 79
68 80
69 81
70 82
71 83
72 84
73 85
74 86
75 87
76 88
77 89
78 90
79 91
80 92
(continued)
2-13
11 Page |
Páginas | Total 23 Páginas | |
PDF Descargar | [ Datasheet AT6010ALV-4QC.PDF ] |
Número de pieza | Descripción | Fabricantes |
AT6010ALV-4QC | Coprocessor Field Programmable Gate Arrays | ATMEL Corporation |
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