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PDF AT875LTS44 Data sheet ( Hoja de datos )
| Número de pieza | AT875LTS44 | |
| Descripción | PHASE CONTROL THYRISTOR | |
| Fabricantes | Power Semiconductors | |
| Logotipo |  |
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ANSALDO
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
PHASE CONTROL THYRISTOR
FINAL SPECIFICATION
apr 97 - ISSUE : 01
AT875LT
Repetitive voltage up to
Mean on-state current
Surge current
4400 V
2200 A
25.2 kA
Symbol Characteristic
BLOCKING
Conditions
Tj
[°C] Value Unit
V RRM
Repetitive peak reverse voltage
120 4400
V
V RSM
Non-repetitive peak reverse voltage
120 4500
V
V DRM
Repetitive peak off-state voltage
120 4400
V
I RRM
Repetitive peak reverse current
V=VRRM
120 200
mA
I DRM
Repetitive peak off-state current
V=VDRM
120 200
mA
CONDUCTING
I T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
2200
A
I T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
1720
A
I TSM
Surge on-state current
sine wave, 10 ms
120 25.2
kA
I² t I² t
without reverse voltage
3175 x1E3 A²s
V T On-state voltage
On-state current = 2000 A
25 2
V
V T(TO)
Threshold voltage
120 1.3
V
r T On-state slope resistance
120 0.334
mohm
SWITCHING
di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1600 A, gate 10V 5ohm 120 200 A/µs
dv/dt
Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM
120 1000
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 40V, 10 ohm , tr=.5 µs 25
3
µs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/µs linear up to 75% VDRM
400 µs
Q rr Reverse recovery charge
di/dt=-20 A/µs, I= 1050 A
120 µC
I rr Peak reverse recovery current
VR= 50 V
A
I H Holding current, typical
VD=5V, gate open circuit
25 300
mA
I L Latching current, typical
VD=12V, tp=30µs
25 1000
mA
GATE
V GT
Gate trigger voltage
VD=12V
25 3.5
V
I GT Gate trigger current
VD=12V
25 400
mA
V GD
Non-trigger gate voltage, min.
VD=2000 V
120 0.8
V
V FGM
Peak gate voltage (forward)
30 V
I FGM
Peak gate current
10 A
V RGM
Peak gate voltage (reverse)
10 V
P GM
Peak gate power dissipation
Pulse width 100 µs
150 W
P G Average gate power dissipation
2W
MOUNTING
R th(j-h)
Thermal impedance, DC
Junction to heatsink, double side cooled
9.5 °C/kW
R th(c-h)
Thermal impedance
Case to heatsink, double side cooled
2 °C/kW
T j Operating junction temperature
F Mounting force
Mass
-30 / 120
40.0 / 50.0
1150
°C
kN
g
ORDERING INFORMATION : AT875LT S 44
standard specification
VDRM&VRRM/100
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet AT875LTS44.PDF ] | |
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