PDF AT88SC101 Data sheet ( Hoja de datos )

Número de pieza	AT88SC101
Descripción	Smart Card ICs 1K E2PROM with Security Logic
Fabricantes	ATMEL Corporation
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No Preview Available ! Features 1K x 1 Serial E2PROM With Security Logic •• Available in Two Memory Organizations: AT88SC10111K x 1Memory Zone AT88SC1022512 x 1Memory Zone Supports ISO/IEC 7816-3 Synchronous Protocol • Stores and Validates Security Codes •• Counts Incorrect Security Code Attempts Provides Transport Code Security • Manufactured Using Low Power CMOS Technology •• VPP Internally Generated • 2 µs Read Access Time; 5 ms Write Cycle Time Temperature Range From -25°C to 70°C •• ESD Immunity > 4K Volts • High Reliability: 100,000 Write/Erase Cycles 100 Years Data Retention Block Diagram Smart Card ICs 1K E2PROM with Security Logic AT88SC101 AT88SC102 Description The AT88SC101/102 family provides 1024 bits of serial E2PROM (Electrically Eras- able and Programmable Read Only Memory) with additional security logic for use in secure smart card applications. The AT88SC101 is available in one 1024 x 1 bit mem- ory zones, and the AT88SC102 is available in two 512 x 1 bit memory zones. ISO Card Configuration ISO Contact C1 C2 C3 C4 C5 C6 C7 C8 Pad # 8 7 6 5 1 2 3 4 Pad Name VCC RST CLK FUS VSS NC I/O PGM Description Operating Voltage Reset Clock and Address Control Identification Fuses Ground No Connect Bi-directional Data Port Programming Control Card Module Contacts Vcc C1 C5 Vss RST C2 C6 N/C CLK C3 C7 I/O FUS C4 C8 PGM 1 page AT88SC101/102 Modes of Operation The AT88SC101/102 has four operation modes selected by PGM, RST, CLK, and by the internal counter: Inputs Micro Instructions PGM RST CLK Definitions RESET X The address counter is reset to 0 and the first bit of the 0 memory is available on I/O after the falling edge of RST and CLK hit 0. Note: The INC instruction is disabled when RST is high (Figure 1). Address counter is reset on the falling edge of RESET. INC (INC/READ) 00 The address counter is incremented and the first bit is available on I/O after the falling edge of the clock (unless reading is forbidden) (Figure 2). Address increments on falling edge of CLK. Data is released after the falling edge of CLK. CMP (INC/CMP) 00 Comparison of the bit presented to the card to the internal bit of the memory (for secret codes only). The bit should stay stable on I/O during the time CLK is low. The address counter is incremented on the falling edge of the CLK (Figure 3). WRITE VERIFY 10 00 I/O must be positioned on 0 for programming or on 1 for erasure before the rising edge of CLK which must stay on 1 for at least 5ms. The bit addressed (which will be written) is available on I/O after the falling edge of the CLK (Figure 4). Notes:1.Output is disabled (Hi state) on addresses where read is disabled. 2.If VDD falls between approximately 3V and 4V the chip will execute a power-on reset. 3.The 2 instructions CMP and UP are coded (0,0) on CLK and PGM. The circuit will distinguish between the 2 instructions by testing the internal address counter (CMP can only be done with the addresses corresponding to the security code or erase key). 4.The internal address counter counts up to 1519 for 101and 1567 for 102. An additional INC sets the counter to 0. 5 5 Page AT88SC101/102 AC Characteristics Die TAMB = –25°C to 70°C, VCC = 5V ± 10%, VSS = 0V (unless otherwise specified). Symbol fCLK tCLK tRH tDVR tCH tCL tDV tOH tSC tHC tCHP tDS tDH tSPR tHPR tDH Characteristics Clock Frequency Clock Cycle Time RST Hold Time Data Valid Reset to Address 0 CLK Pulse Width (High) CLK Pulse Width (Low) Data Access Data Hold Data In Setup (CMP Instruction) Data In Hold (CMP Instruction) CLK Pulse Width (High in Programming) Data In Setup Data In Hold PGM Setup PGM Hold Data Hold from CLK Min — 3.3 20 — 0.2 0.2 — 0 0 0.2 5.0 0.2 0 2.2 0.2 0 Typ — — — — — — — — — — — — — — — — Max 300 — — 2.0 — — 2.0 — — — — — — — — — Unit KHz µs µs µs µs µs µs µs µs µs ms µs µs µs µs µs Conditions of Dynamic Tests The circuit has an output with open drain. An external re- sistance is thus necessary between VCC and I/O in order to load the output. Pulse Levels of the Input:VSS to 3.0V Reference Levels in Output:1.5V Rising and Falling Time of Signals:< 5ns VCC 4.7K CHIP TEST POINT I/O 100 pF Test Circuit Included 11 11 Page

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