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PDF AT89C51ID2 Data sheet ( Hoja de datos )

Número de pieza AT89C51ID2
Descripción 8-bit Flash Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Features
80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 bytes Scratch Pad RAM
– 10 Interrupt Sources With 4 Priority Levels
ISP (In-System Programming) Using Standard VCC Power Supply
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
– In X2 Mode (6 Clocks/Machine Cycle)
20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
64K bytes On-chip Flash Program/Data Memory
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 bytes)
– 768 bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 bytes EEPROM block for Data Storage
– 100k Write Cycles
Dual Data Pointer
32 KHz Crystal Oscillator
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independant Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
Two Wire Interface 400K bit/s
Programmable Counter Array with:
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag
Power Control Modes: Idle Mode, Power-down Mode
Power Supply: 2.7V to 5.5V
Temperature Ranges: Industrial (-40 to +85°C)
Packages: PLCC44, VQFP44
8-bit Flash
Microcontroller
AT89C51ID2
Description
AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single
chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program
and for data.
The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
4289C–8051–11/05
1

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AT89C51ID2 pdf
Table 2. C51 Core SFRs
Mnemonic Add Name
ACC
E0h Accumulator
B F0h B Register
PSW
D0h Program Status Word
SP 81h Stack Pointer
DPL
82h Data Pointer Low byte
DPH
83h Data Pointer High byte
Table 3. System Management SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
AUXR1
CKRL
CKSEL
OSCON
CKCKON0
CKCKON1
A2h Auxiliary Register 1
97h Clock Reload Register
85h Clock Selection Register
86h Oscillator Control Register
8Fh Clock Control Register 0
AFh Clock Control Register 1
76543210
CY AC F0 RS1 RS0 OV F1
P
76
SMOD1 SMOD0
5
-
4
POF
- - M0
-
-
-
-
TWIX2
-
-
ENBOO
T
--
--
--
WDTX2 PCAX2
--
-
-
-
-
SIX2
-
3
GF1
XRS1
2
GF0
XRS0
1
PD
EXTRA
M
0
IDL
AO
GF3 0
- DPS
-
-
-
T2X2
-
---
- - CKS
SCLKT0 OscBEn OscAEn
T1X2
T0X2
X2
- - SPIX2
Table 4. Interrupt SFRs
Mnemonic Add Name
76543210
IEN0
A8h Interrupt Enable Control 0
EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1
B1h Interrupt Enable Control 1
-
-
-
-
-
ESPI
ETWI
EKBD
IPH0
B7h Interrupt Priority Control High 0
-
PPCH PT2H
PSH
PT1H
PX1H
PT0H
PX0H
IPL0
B8h Interrupt Priority Control Low 0
-
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
IPH1
B3h Interrupt Priority Control High 1
-
-
-
-
- SPIH IE2CH KBDH
IPL1
B2h Interrupt Priority Control Low 1
-
-
-
-
-
SPIL
IE2CL KBDL
5 AT89C51ID2
4289C–8051–11/05

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AT89C51ID2 arduino
Table 15. Pin Description
Pin Number
Mnemonic
PLCC44 VQFP44
VSS 22 16
VCC 44 38
P0.0 - P0.7
43 - 36
37 - 30
P1.0 - P1.7
2-9
40 - 44
1-3
2 40
3 41
4 42
5 43
6 44
71
82
93
Type
I
I
I/O
I/O
I/O
I/O
I
I/O
I
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name and Function
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down opera-
tion
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or
VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed
low-order address and data bus during access to external program and data memory. In
this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code
bytes during EPROM programming. External pull-ups are required during program verifica-
tion during which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source current because of the internal
pull-ups. Port 1 also receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51ID2 Port 1 include:
P1.0: Input/Output
T2 (P1.0): Timer/Counter 2 external count input/Clockout
XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier
P1.1: Input/Output
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
SS: SPI Slave Select
P1.2: Input/Output
ECI: External Clock for the PCA
P1.3: Input/Output
CEX0: Capture/Compare External I/O for PCA module 0
P1.4: Input/Output
CEX1: Capture/Compare External I/O for PCA module 1
P1.5: Input/Output
CEX2: Capture/Compare External I/O for PCA module 2
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in
slave mode, MISO outputs data to the master controller.
P1.6: Input/Output
CEX3: Capture/Compare External I/O for PCA module 3
SCK: SPI Serial Clock
P1.7: Input/Output:
CEX4: Capture/Compare External I/O for PCA module 4
11 AT89C51ID2
4289C–8051–11/05

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