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PDF AT89C51RB2 Data sheet ( Hoja de datos )
| Número de pieza | AT89C51RB2 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
• Variable Length MOVX for Slow RAM/Peripherals
• ISP (In-system Programming) Using Standard VCC Power Supply
• Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
• High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– 16K/32K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100K Write Cycles
• On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 Bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
• Keyboard Interrupt Interface on Port P1
• SPI Interface (Master/Slave Mode)
• 8-bit Clock Prescaler
• Improved X2 Mode with Independent Selection for CPU and Each Peripheral
• Programmable Counter Array 5 Channels
– High-speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
• Asynchronous Port Reset
• Full Duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (Inhibit ALE)
• Hardware Watchdog Timer (One-time Enabled with Reset-out)
• Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
• Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
• Packages: PDIL40, PLCC44, VQFP44
8-bit
Microcontroller
with 16K/
32K Bytes Flash
AT89C51RB2
AT89C51RC2
Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro-
controllers. It contains a 16K or 32K Bytes Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
Rev. 4180E–8051–10/06
1 page  
AT89C51RB2/RC2
Table 2. C51 Core SFRs
Mnemonic Add Name
ACC
E0h Accumulator
B F0h B Register
PSW
D0h Program Status Word
SP 81h Stack Pointer
DPL
82h Data Pointer Low Byte
DPH
83h Data Pointer High Byte
76543210
CY
AC
F0
RS1
RS0
OV
F1
P
Table 3. System Management SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
AUXR1
A2h Auxiliary Register 1
CKRL
97h Clock Reload Register
CKCKON0 8Fh Clock Control Register 0
CKCKON1 AFh Clock Control Register 1
7
SMOD1
DPU
-
CKRL7
-
-
6
SMOD0
-
-
CKRL6
WDTX2
-
5
-
M0
ENBOOT
CKRL5
PCAX2
-
4
POF
XRS2
-
CKRL4
SIX2
-
3
GF1
XRS1
GF3
CKRL3
T2X2
-
2
GF0
XRS0
0
CKRL2
T1X2
-
1
PD
EXTRAM
-
CKRL1
T0X2
-
0
IDL
AO
DPS
CKRL0
X2
SPIX2
Table 4. Interrupt SFRs
Mnemonic Add Name
76543210
IEN0
A8h Interrupt Enable Control 0
EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1
B1h Interrupt Enable Control 1
-
-
-
-
-
ESPI
EI2C
KBD
IPH0
B7h Interrupt Priority Control High 0
-
PPCH
PT2H
PHS
PT1H
PX1H
PT0H
PX0H
IPL0
B8h Interrupt Priority Control Low 0
-
PPCL
PT2L
PLS
PT1L
PX1L
PT0L
PX0L
IPH1
B3h Interrupt Priority Control High 1
-
-
-
-
- SPIH IE2CH KBDH
IPL1
B2h Interrupt Priority Control Low 1
-
-
-
-
-
SPIL
IE2CL KBDL
Table 5. Port SFRs
Mnemonic Add Name
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
76543210
4180E–8051–10/06
5
5 Page 
AT89C51RB2/RC2
Table 12. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number
Mnemonic
DIL LCC VQFP44 1.4 Type Name and Function
I/O CEX4: Capture/Compare External I/O for PCA Module 4
P1.0 - P1.7
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data from the master controller.
XTAL1
19 21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18 20
14
O Crystal 2: Output from the inverting oscillator amplifier
P2.0 - P2.7
21 - 28 24 - 31
18 - 25
I/O Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high - order address Byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some
Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32KB devices
P3.0 - P3.7
10 - 17 11,
13 - 19
5,
7 - 13
I/O Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
10 11
5
I RXD (P3.0): Serial input port
11 13
7
O TXD (P3.1): Serial output port
12 14
8
I INT0 (P3.2): External interrupt 0
13 15
9
I INT1 (P3.3): External interrupt 1
14 16
10
I T0 (P3.4): Timer 0 external input
15 17
11
I T1 (P3.5): Timer 1 external input
16 18
12
O WR (P3.6): External data memory write strobe
17 19
13
O RD (P3.7): External data memory read strobe
RST
9 10
4
Reset: A high on this pin for two machine cycles while the oscillator is running,
I/O
resets the device. An internal diffused resistor to VSS permits a power-on reset using
only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
ALE/PROG
30 33
27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low Byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR. 0
bit. With this bit set, ALE will be inactive during internal fetches.
4180E–8051–10/06
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT89C51RB2.PDF ] | |
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