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PDF AT89LS51 Data sheet ( Hoja de datos )
| Número de pieza | AT89LS51 | |
| Descripción | 8-bit Low-Voltage Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Compatible with MCS®-51 Products
• 4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 10,000 Write/Erase Cycles
• 2.7V to 4.0V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Flexible ISP Programming (Byte and Page Mode)
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT89LS51 is a low-voltage, high-performance CMOS 8-bit microcontroller with
4K bytes of in-system programmable Flash memory. The device is manufactured
using Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the pro-
gram memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with in-system programma-
ble Flash on a monolithic chip, the Atmel AT89LS51 is a powerful microcontroller
which provides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89LS51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89LS51 is designed with static logic for opera-
tion down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port, and interrupt system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator, disabling all other chip functions until the next
external interrupt or hardware reset.
8-bit
Low-Voltage
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
AT89LS51
3053C–MICRO–6/08
1 page  
AT89LS51
4.6 Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89LS51, as shown in the
following table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
4.7 RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.
4.8 ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.9 PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89LS51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
3053C–MICRO–6/08
5
5 Page 
AT89LS51
10. Interrupts
The AT89LS51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 10-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 10-1 shows that bit positions IE.5 and IE.6 are unimplemented. User software
should not write 1s to these bit positions, since they may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle.
.
Table 10-1. Interrupt Enable (IE) Register
(MSB)
(LSB)
EA – – ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
Disables all interrupts. If EA = 0, no interrupt is
EA
IE.7
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
– IE.6 Reserved
– IE.5 Reserved
ES IE.4 Serial Port interrupt enable bit
ET1 IE.3 Timer 1 interrupt enable bit
EX1 IE.2 External interrupt 1 enable bit
ET0 IE.1 Timer 0 interrupt enable bit
EX0 IE.0 External interrupt 0 enable bit
User software should never write 1s to reserved bits, because they may be used in future AT89 products.
3053C–MICRO–6/08
11
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