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PDF AT89S4D12-12JC Data sheet ( Hoja de datos )
| Número de pieza | AT89S4D12-12JC | |
| Descripción | 8-Bit Microcontroller with 132K Bytes Flash Data Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT89S4D12
Features
• Compatible with MCS-51™ Products
• 128K Bytes of In-System Reprogrammable Flash data memory and 4K Bytes of
Downloadable Flash Program Memory
– Endurance: 1,000 Write/Erase Cycles per Sector
– Data Retention: 10 Years
• Sector Programming: 128 Bytes/Sector
• Single 3.3V ± 10% Supply
• On-Chip 12 MHz oscillator
• Two-Level Program Memory Lock
• 256-Bytes Internal RAM
• 5 Programmable I/O Lines
• Serial Peripheral Interface (SPI) Channel
• Serial Program Downloading
• Dual Data Pointer Registers
Description
The AT89S4D12 is a low-voltage, highly integrated CMOS 8-bit microcomputer with
4K bytes of downloadable Flash program memory and 128K bytes of in-system repro-
grammable Flash data memory. The device is manufactured using Atmel’s high den-
sity Flash memory technology and is compatible with the industry-standard MCS-51™
instruction set.
The 128K bytes of on-chip Flash data memory are accessed as two 64K byte blocks.
Bit 0 at SFR location 96H is used to select the active block. The MOVX instruction is
used to read and write the data memory. Both the program and data memory arrays
can be programmed by an external programmer.
The downloadable Flash can be changed one page (128 bytes) at a time and is
accessible through the SPI serial peripheral interface port. Holding RESET active
forces the SPI bus into a slave input mode and allows the program memory to be writ-
ten-from or read-to unless Lock Bit 2 has been activated.
The functional operations of the 128K bytes Flash data memory are equivalent to
those on the AT29LV010A 1M Bit Flash memory device.
8-Bit
Microcontroller
with
132K Bytes
Flash Data
Memory
AT89S4D12
Pin Configurations
SOIC Top View
PLCC Top View
GND
TEST1
RESET
SDI/P1.1
SDO/P1.0
TEST2
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 P1.2/DTR
26 P1.3/SCK
25 P1.4/DSR
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
P1.0/SDO
TEST2
NC
NC
NC
NC
NC
NC
NC
5
6
7
8
9
10
11
12
13
29 P1.4/DSR
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
0921A-A–12/97
4-281
1 page  
AT89S4D12
Table 2. MCON—Memory Control Register
MCON Address = 96H
---
Bit 7 6 5
-
4
Reset Value = XXXX X010B
-
DPS
RDY/BSY
A16
3210
Symbol
DPS
RDY/BSY
A16
Function
Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register,
DP0, and DPS = 1 selects the second bank, DP1.
DataFlash Ready/Busy Flag. This bit serves as the RDY/BSY flag in a Read-Only mode
during DataFlash write. RDY/BSY = 1 means that the DataFlash is ready to be
programmed. While programming operations are being executed, the RDY/BSY bit
equals `0' and is automatically reset to `1' when programming is completed.
Memory Block Select. A16 = 0 selects the lower 64K bytes DataFlash memory block.
A16 = 1 selects the upper 64K bytes DataFlash block.
Table 3. SPCR—SPI Control Register
SPCR Address = D5H
Reset Value = 000X 01XXB
SPIE
SPE
DORD
-
CPOL
CPHA
SPR1
SPR0
Bit 7 6 5 4 3 2 1 0
Symbol
SPIE
SPE
DORD
CPOL
CPHA
SPR0
SPR1
Function
SPI Interrupt Enable. This bit, enables SPI interrupts: SPIE = 1 enable SPI interrupts. SPIE = 0 disables
SPI interrupts.
SPI Enable. SPI = 1 enables the SPI channel and connects SDO, SDI and SCK to pins P1.0, P1.1, and
P1.3. SPI = 0 disables the SPI channel.
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data
transmission.
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is
low when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between
master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1
and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency,
FOSC., is as follows:
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = FOSC. divided by
4
16
64
128
4-285
5 Page 
AT89S4D12
Flash Memory Serial Programming Circuit
INSTRUCTION
INPUT
DATA OUTPUT
CLOCK IN
RDY/BUSY
SDI/P1.1
SDO/P1.0
SCK/P1.3
DSR/P1.4
TEST2
GND
3.3V
VCC
RESET
TEST1
Reading the Signature Bytes
The signature bytes are read by executing the Read Signa-
ture command at locations 30H and 31H. The values
returned are as follows:
(30H) = 1EH indicates manufactured by Atmel
(31H) = 84H indicates AT89S4D12
Serial Downloading Waveforms
SERIAL CLOCK INPUT
SCK/P1.3
76543210
SERIAL DATA INPUT MSB
SDI/P1.1
LSB
SERIAL DATA OUTPUT MSB
SDO/P1.0
LSB
1ST INSTRUCTION
BYTE 1 BYTE 2 BYTE 3 BYTE 4
2ND INSTRUCTION
BYTE 1 BYTE 2 BYTE 3 BYTE 4
tBLC = 300 µS MAX.
4-291
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