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PDF AT90S2313 Data sheet ( Hoja de datos )
| Número de pieza | AT90S2313 | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
• Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
– Full Duplex UART
• • Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
• • Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.8 mA
– Idle Mode: 0.8 mA
– Power-down Mode: <1 µA
• I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
• Operating Voltages
– 2.7 - 6.0V (AT90S2313-4)
– 4.0 - 6.0V (AT90S2313-10)
• Speed Grades
– 0 - 4 MHz (AT90S2313-4)
– 0 - 10 MHz (AT90S2313-10)
Pin Configuration
PDIP/SOIC
8-bit
Microcontroller
with 2K Bytes
of In-System
Programmable
Flash
AT90S2313
Rev. 0839I–AVR–06/02
1
1 page  
Architectural
Overview
AT90S2313
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single clock cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Figure 4. The AT90S2313 AVR RISC Architecture
0839I–AVR–06/02
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up func-
tion. These added function registers are the 16-bit X-register, Y-register, and Z-register.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S2313 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the Register File as well. This is enabled by the fact that the Register File is
assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.
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5 Page 
Data Direct
AT90S2313
Operand address is contained in 6 bits of the instruction word. n is the destination or
source register address.
Figure 12. Direct Data Addressing
Data Indirect with
Displacement
A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify
the destination or source register.
Figure 13. Data Indirect with Displacement
Data Indirect
Operand address is the result of the Y- or Z-register contents added to the address con-
tained in 6 bits of the instruction word.
Figure 14. Data Indirect Addressing
0839I–AVR–06/02
Operand address is the contents of the X-, Y-, or Z-register.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT90S2313.PDF ] | |
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