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PDF AT91FR4042 Data sheet ( Hoja de datos )
| Número de pieza | AT91FR4042 | |
| Descripción | AT91 ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 256K Bytes of On-chip SRAM (2 Mbits)
– 32-bit Data Bus, Single-clock Cycle Access
• 256K Words 16-bit Flash Memory (4 Mbits)
– Single Voltage Read/Write
– Sector Erase Architecture
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Factory-programmed AT91 Flash Uploader Software
• Fully Programmable External Bus Interface (EBI)
– Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
• Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripherals can be Deactivated Individually
• Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C
• 2.7V to 3.6V I/O and Flash Operating Range, 1.65V to 1.95V Core Operating Range
• -40°C to 85°C Temperature Range
• Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
AT91 ARM®
Thumb®
Microcontrollers
AT91FR4042
Description
The AT91FR4042 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR4042 ARM microcontroller features 2 Mbits of on-chip SRAM and 4 Mbits
of Flash memory in a single compact 121-ball BGA package. Its high level of integra-
tion and very small footprint make the device ideal for space-constrained applications.
The high-speed on-chip SRAM enables a performance of up to 63 MIPs and signifi-
cant power reduction over an external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-pro-
grammed Flash Uploader using a single device supply, making the AT91FR4042
suitable for in-system programmable applications.
2648D–ATARM–03/04
1 page  
Block Diagram
Figure 2. AT91FR4042
AT91FR4042
2648D–ATARM–03/04
5
5 Page 
Remap Command
Abort Control
External Bus Interface
Flash Memory
2648D–ATARM–03/04
AT91FR4042
The BMS pin is multiplexed with the I/O line P24 that can be programmed after reset like
any standard PIO line.
Table 3. Boot Mode Select
BMS
Boot Memory
1 External 8-bit memory on NCS0
0 External 16-bit memory on NCS0
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91FR4042 uses
a remap command that enables switching between the boot memory and the internal
primary SRAM bank addresses. The remap command is accessible through the EBI
User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing
a remap command is mandatory if access to the other external devices (connected to
chip selects 1 to 7) is required. The remap operation can only be changed back by an
internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI
is asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal
peripherals, whether the address is defined or not.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and
can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte,
half-word and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit
device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-
bit memory (Byte Write Access Mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in
the case of single-clock cycle access.
In the AT91FR4042, the External Bus Interface connects internally to the Flash memory.
The 4-Mbit Flash memory is organized as 262144 words of 16 bits each. The Flash
memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A18.
The address, data and control signals, except the Flash memory enable, are internally
interconnected. The user should connect the Flash memory enable (NCSF) to one of
the active-low chip selects on the EBI; NCS0 must be used if the Flash memory is to be
the boot memory. In addition, if the Flash memory is to be used as boot memory, the
BMS input must be pulled down externally in order for the processor to perform correct
16-bit fetches after reset.
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| PDF Descargar | [ Datasheet AT91FR4042.PDF ] | |
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