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PDF AT91FR4081-33CI Data sheet ( Hoja de datos )
| Número de pieza | AT91FR4081-33CI | |
| Descripción | AT91 ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 136K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
• 512K Words 16-bit Flash Memory (8 Mbits)
– Single Voltage Read/Write, 110 ns Access Time
– Sector Erase Architecture
– Fast Word Program Time of 20 µs; Fast Sector Erase Time of 200 ms
– Dual-plane Organization Allows Concurrent Read and Program/Erase
– Erase Suspend Capability
– Low-power Operation: 25 mA Active, 10 µA Standby
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– Factory-programmed AT91 Flash Uploader Software
• Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
• Fully Static Operation:
– 0 Hz to 33 MHz Internal Frequency Range at 3.0V, 85°C
• 2.7V to 3.6V Operating Range
• -40°C to 85°C Temperature Range
• Available in a 120-ball BGA Package
Description
The AT91FR4081 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The eight-level priority-vectored interrupt controller, together with the Peripheral Data
Controller, significantly enhance real-time device performance.
By combining the microcontroller, featuring more than 1 Mbit of on-chip SRAM and a
wide range of peripheral functions, with 8 Mbits of Flash memory in a single compact
120-ball BGA package, the Atmel AT91FR4081 provides a powerful, flexible and cost-
effective solution to many compute-intensive embedded control applications and
offers significant board size and system cost reductions.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-pro-
grammed Flash Uploader using a single device supply, making the AT91FR4081 ideal
for in-system programmable applications.
AT91 ARM®
Thumb®
Microcontrollers
AT91FR4081
Rev. 1386C–ATARM–02/02
1
1 page  
TMS
TDO
TDI
TCK
VDD
GND
NRST
MCKI
P25/MCKO
P12/FIQ
P9/IRQ0
P10/IRQ1
P11/IRQ2
P13/SCK0
P14/TXD0
P15/RXD0
P20/SCK1
P21/TXD1/NTRI
P22/RXD1
P16
P17
P18
P19
P23
P24/BMS
NWDOVF
Embedded
ICE
ARM7TDMI Core
ASB
D0 - D15
A1 - A20
Reset
RAM
8K Bytes
Clock
ASB
Controller
AMBA Bridge
AIC: Advanced
EBI User
Interrupt Controller
Interface
OE WE
APB
GND
VPP
USART0
2 PDC
Channels
MCU
VCC
FLASH MEMORY VCCQ
P
I
O
USART1
2 PDC
Channels
AT91M40800
P
I
O
AT49BV1604/1614
BYTE
RESET
RDY/BUSY
CE
PS: Power Saving
Chip ID
WD: Watchdog Timer
PIO: Parallel I/O Controller
TC: Timer
Counter
TC0
TC1
TC2
D0-D15
A1-A19
A0/NLB
NWR1/NUB
NWAIT
NCS0
NCS1
NRD/NOE
NWR0/NWE
P26/NCS2
P27/NCS3
P28/A20/CS7
P29/A21/CS6
P30/A22/CS5
P31/A23/CS4
GND
VPP
VDD
VDD
VDD
NRSTF
NBUSY
NCSF
P0/TCLK0
P3/TCLK1
P6/TCLK2
P1/TIOA0
P2/TIOB0
P4/TIOA1
P5/TIOB1
P7/TIOA2
P8/TIOB2
5 Page 
AT91FR4081
Abort Control
External Bus Interface
Flash Memory
The remap command is accessible through the EBI User Interface by writing one in RCB of
EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to
the other external devices (connected to chip selects 1 to 7) is required. The remap operation
can only be changed back by an internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can be
configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte, half-word
and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte
Access Select Mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte
Write Access Mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in the case
of single-clock cycle access.
In the AT91FR4081, the External Bus Interface connects internally to the Flash memory.
The 8-Mbit Flash memory is organized as 524,288 words of 16 bits each. The Flash memory
is addressed as 16-bit words via the EBI. It uses address lines A1 - A19.
The address, data and control signals, except the Flash memory enable, are internally inter-
connected. The user should connect the Flash memory enable (NCSF) to one of the active-
low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot mem-
ory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be
pulled down externally in order for the processor to perform correct 16-bit fetches after reset.
During boot, the EBI must be configured with correct number of standard wait states. For
example, five standard wait states are required when the microcontroller is running at 40 MHz.
The user must ensure that all VDD and all GND pins are connected to their respective sup-
plies by the shortest route. The Flash memory powers-on in the read mode. Command
sequences are used to place the device in other operating modes, such as program and
erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high level,
the memory is in its standard operating mode; a low level on this input halts the current mem-
ory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of
the written data on I/O7. An open-drain NBUSY output pin provides another method of detect-
ing the end of a program or erase cycle. This pin is pulled low while program and erase cycles
are in progress and is released at the completion of the cycle. A toggle bit feature provides a
third means of detecting the end of a program or erase cycle.
1386C–ATARM–02/02
11
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| PDF Descargar | [ Datasheet AT91FR4081-33CI.PDF ] | |
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